Timer circuit and semiconductor memory incorporating the timer circuit

A semiconductor memory device having:

• memory cells dynamically storing data;
• and
• a timer circuit generating a signal which defines a refresh cycle of said memory cells,
• wherein a cycle of said signal is controlled in accordance with a temperature-dependency of data holding time of said memory cells, and wherein said timer circuit further includes a circuit that controls a variable temperature-dependency of said cycle of said signal using a rectifying device having at least one diode that is controlled to perform rectifying operations for changing said variable temperature dependency, a power circuit for generating a power current in response to a current flowing through said rectifying device, and a clock generating circuit for receiving a supply of a power from said power circuit and generating a clock signal.

A semiconductor memory device, comprising:

• memory cells dynamically storing data;
• and
• a timer circuit generating a signal which defines a refresh cycle of said memory cells.
• wherein a cycle of said signal is controlled in accordance with a temperature-dependency of data holding time of said memory cells.
• wherein said timer circuit comprises a rectifying device with a temperature-dependent current characteristic, a power circuit for generating a power current in response to a current flowing through said rectifying device, and a clock generating circuit for receiving a supply of a power from said power circuit and generating a clock signal, and
• wherein said rectifying device has a temperature characteristic varying circuit, and said temperature characteristic varying circuit includes a plurality of diodes connected in series and a by-pass circuit connected in parallel to each of said plurality of diodes, and a conductive state or a non-conductive state of said by-pass circuit is controlled to change the number of said diodes connected to perform rectifying operations for changing a temperature-dependency of said cycle of said signal.

A semiconductor memory device with a word pulse generating circuit which has:

• a rectifying device with a variable temperature-dependent current characteristic;
• a power circuit for generating a power current in response to a current flowing through said rectifying device;
• and
• a delay circuit receiving a power supply from said power circuit and delaying a trigger signal for a word pulse,
• wherein said rectifying device includes a diode connected in series to a power supply, a resistance connected in series between said diode and a ground, and a MOS transistor connected in parallel to said resistance, and a conductive state or a non-conductive state of said MOS transistor is controlled by a state control signal which switches the device between in a stand-by state and in an active state.

A timer circuit, comprising:

• a first current mirror circuit connected between a power voltage and a grand voltage and a current path of a primary side of the current mirror circuit passes through said power voltage, a first conductivity-type MOS transistor;
• and another first conductivity-type MOS transistor and said grand voltage;
• a temperature dependency providing circuit including a diode connected between the power voltage and the primary side of the first current mirror circuit and connected in series to a resistance to provide a function of a load at the primary side of the first current mirror circuit and a temperature independency and to supply to the first current mirror circuit through the first conductivity-type MOS transistor a primary side current flowing through the power voltage, the diode, the resistance and a second conductivity-type MOS transistor;
• and
• a clock generating circuit which is connected to a secondary side of the first current mirror circuit to generate a clock signal having a cycle depending upon temperature according to the secondary current flowing to the secondary side of the first current mirror circuit, wherein a current path flowing through the diode and the resistance of the temperature dependency providing circuit presents outside the primary side current path of the first current mirror circuit.