Semiconductor memory device for enhancing bitline precharge time

A semiconductor memory device, comprising:

• a memory cell array configured as a plurality of memory cell blocks of memory cells, the memory cells connected to one another at points crossed between a plurality of word lines and a plurality of bitlines;
• a sense amplifier connected to the memory cells via a bitline pair;
• an isolation part connected to the bitline pair for electrically connecting a memory cell to, or isolating the memory cell from, the sense amplifier;
• an equalizer connected to the bitline pair between the isolation part and a memory cell block for precharging, in a precharge mode, each bitline of the bitline pair to the same voltage;
• an isolation control signal generator applying an isolation control signal to the isolation part;
• and
• a control signal delay delaying the isolation control signal for a given time from a precharge starting time point of the equalizer,
• the isolation control signal generator applying the isolation control signal at an internal supply voltage level that is lower than a specified high voltage level.

A method of accelerating a precharge time in a semiconductor memory device, comprising:

• applying an equalization enable signal to an equalizer at initiation of a precharge mode to precharge a bitline pair connecting a memory cell block to a sense amplifier;
• and
• delaying isolation control signals by a given time in the precharge mode, and
• applying the isolation control signals to isolation parts adapted to connect the memory cell block to or isolate the memory cell block from the sense amplifier, so that a time of applying the isolation control signals is after a time of applying the equalization enable signal.