Test structure for measuring a junction resistance in a DRAM memory cell array

An improved test structure for determining a resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array, wherein:

• the matrix cell array has active regions of selection transistors arranged in rows along a first direction and storage capacitors arranged in rows along a second direction perpendicular to the first direction;
• and
• conducting junctions between the active regions of the selection transistors and the storage capacitors are formed at overlapping areas of the rows running perpendicular to one another in each case in a single edge region of the overlapping area in the first direction;
• the improvement which comprises:
• the active regions of the selection transistors and/or the storage capacitors are connected by connecting structures selected from the group consisting of tunnel structures and bridge structures in the second direction in the region adjoining the junction to be measured between the active region of the selection transistor and the storage capacitor, for attaining a low-impedance connection to the junction to be measured.