Semiconductor memory device

A semiconductor memory device comprising:

• simultaneously activated first and second memory arrays each having a plurality of memory cells, a plurality of normal row elements each defined in said memory arrays as a group of memory cells arranged in a row direction, and a plurality of normal column elements each defined in said memory arrays as a group of memory cells arranged in a column direction;
• redundant row elements disposed in correspondence with said first and second memory arrays to be used for defective normal row element replacement in the respective memory arrays independently of each other;
• and
• redundant column elements disposed in correspondence with said first and second memory arrays in such a manner that at least one of them corresponds to each said memory array while intersecting said redundant row element disposed in correspondence with a corresponding memory array and used for defective normal column element replacement independently of each other, wherein
• a row repair region defined as a group of normal row elements with permission for replacement by each said redundant row element disposed in correspondence with one of said first and second memory arrays and a column repair region defined as a group of normal column elements with permission of replacement by use of each said redundant column element disposed in correspondence with the remaining one of said memory arrays are set to have an overlap region in which said row and column repair regions are at least partially overlapped each other.

A semiconductor memory device comprising:

• a cell array having a plurality of memory cells;
• a plurality of main word lines disposed in said cell array;
• a plurality of sub-word lines simultaneously selectable upon activation of each said main word line, each said sub-word line being for selecting more than one memory cell disposed within a specified range in a row direction;
• a plurality of column select lines for execution of memory cell selection in association with each of said sub-word line;
• at least one spare main word line disposed for repairing a defective cell;
• and
• a plurality of spare sub-word lines simultaneously selected by said spare main word line, each of said spare sub-word lines being for performing spare cell selection within a specified range in the row direction, wherein
• when any one of said plurality of sub-word lines selected by a certain main word line is found defective, the defective sub-word line is made inactive while letting a presently selected main word line stay active, whereas said spare main word line is activated, thereby permitting activation of one of a plurality of spare sub-word lines, as selected by this spare main word line, which is used for replacement of the defective sub-word line.

A semiconductor memory device comprising:

• a cell array having a plurality of memory cells, a plurality of normal row elements each defined in said cell array as a group of memory cells arranged in a row direction, and a plurality of normal column elements each defined in said cell array as a group of memory cells arranged in a column direction;
• a plurality of redundant row elements disposed for repairing more than one defective normal row element of said cell array;
• and
• a plurality of redundant column elements disposed for repairing more than one defective normal column element of said cell array, wherein
• at least two first and second row repair regions, each of which is defined as a group of normal row elements with permission of replacement by each said redundant row element, are set to have different cell capacities with each other, and
• repair efficiency in each column repair region defined as a group of normal column elements with permission of replacement by each of said plurality of redundant column elements is set to become equal to one another within said cell array.