Redundancy in series grouped memory architecture
AssigneeInfineon Technologies AG
InventorsNorbert Rehm, Hans-Oliver Joachim, Thomas Roehr, Joerg W. Wohlfahrt
Life of this patent
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Abstract
An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory chain. As such, a redundant cell is used to repair a defective cell within the chain. This eliminates the need in conventional chained architecture to replace the whole memory block when there is a defective cell.
Claims25
An integrated circuit comprising:
- x first memory cells, where x is greater than or equal to 2, the first memory cells serve as storage memory cells;
- m second memory cells, where m is equal to or greater than 1, the second memory cells serve as redundant memory cells, wherein a second memory cell is used to repair a defective first memory cell;
- and
- the first and second memory cells, each comprises a transistor coupled to a capacitor in parallel, are coupled in series to form a group, wherein providing the second memory cells within a same group as the first memory cells enables replacement of the defective first memory cell without the need for block replacement.
The integrated circuit 7 further comprises a plurality of the bitline pairs to form a memory block.
The integrated circuit 9 further comprises a plurality of the bitline pairs to form a memory block.
The integrated circuit 11 further comprises a plurality of the bitline pairs to form a memory block.
The integrated circuit 14 further comprises a plurality of the bitline pairs to form a memory block.
The integrated circuit 16 further comprises a plurality of the bitline pairs to form a memory block.
A method of redundancy in a memory array comprising:
- providing first memory cells for storing data;
- providing second memory cells, the second memory cells serving as redundant cells;
- coupling the first and second memory cells in series to form a group;
- and
- in the event one of the first memory cells is defective, replacing the first defective memory cell with one of the second memory cells, wherein providing both first and second memory cells in a same group enables replacement of a defective first memory cell without the need for block replacement.
Dependencies are inferred from the claim text.