Semiconductor memory device
AssigneesRenesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
InventorsHiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
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Abstract
Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
Claims6
A semiconductor memory device comprising:
- a pair of first data transmission lines;
- and
- a second data transmission line,
- wherein said pair of first data transmission lines are formed in a first layer on the main face of a semiconductor substrate and arranged to extend in a first direction of said main face,
- wherein said second data transmission line is formed in a second layer which is different from said first layer and is arranged to extend in said first direction,
- wherein said second data transmission line is so arranged as to substantially equalize a capacitance between one of said pair of first data transmission lines and said second data transmission line to a capacitance between the other of said pair of first data transmission lines and said second data transmission line, and
- wherein said pair of first data transmission lines is positioned underneath said second data transmission line.
Dependencies are inferred from the claim text.