Signal integrity checking circuit

A signal integrity checking circuit, comprising:

• a plurality of storage elements positioned adjacent to each other on an integrated circuit substrate, each of said storage elements having a clock input, a data input and a data output, the clock inputs of all of said storage elements connected to a common clock signal line, the data inputs of all of said storage elements being coupled to a common data input line for receiving data to be loaded therein;
• a logic gate having a set of inputs coupled to the data outputs of each of said storage elements and having an output providing a flag signal as an output of the signal integrity checking circuit;
• and
• a first inverter connected between said data input line and the data input of one of said storage elements, and a second inverter connected between the data output of the same said storage element and an input of the logic gate.

A signal integrity checking circuit, comprising:

• a plurality of storage elements positioned adjacent to each other on an integrated circuit substrate, each of said storage elements having a clock input, a data input and a data output, the clock inputs of all of said storage elements connected to a common clock signal line, the data inputs of all of said storage elements being coupled to a common data input line for receiving data to be loaded therein;
• and
• a logic gate having a set of inputs coupled to the data outputs of each of said storage elements and having an output providing a flag signal as an output of the signal integrity checking circuit;
• wherein said logic gate is a NAND gate, and said initial data has a logic “1” state, said flag signal having a logic “0” state under a normal signal condition but having a logic “1” state in response to a poor signal integrity condition.

A signal integrity checking circuit, comprising:

• a pair of flip-flops positioned immediately adjacent to each other on an integrated circuit substrate, both flip-flops having a clock input, a data input and a data output, the clock inputs of both flip-flops connected to a common clock signal line, the data inputs of both flip-flops being coupled to a common data input line for receiving data to be loaded therein;
• a logic gate having a pair inputs coupled to the data outputs of both flip-flops and having an output providing a flat signal as an output of the signal integrity checking circuit;
• and
• a first inverter connected between said data input line and the data input of one of said flip-flops, and a second inverter connected between the data output of the same said flip-flop and an input of the logic gate.

A signal integrity checking circuit, comprising:

• a pair of flip-flops positioned immediately adjacent to each other on an integrated circuit substrate, both flip-flops having a clock input, a data input and a data output, the clock inputs of both flip-flops connected to a common clock signal line, the data inputs of both flip-flops being coupled to a common data input line for receiving data to be loaded therein;
• and
• a logic gate having a pair inputs coupled to the data outputs of both flip-flops and having an output providing a flag signal as an output of the signal integrity checking circuit;
• wherein said logic gate is a NAND gate, and said initial data has a logic “1” state, said flag signal having a logic “0” state under a normal signal condition but having a logic “1” state in response to a poor signal integrity condition.