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US 6,856,555 B2Granted
Leak immune semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorYukihiro Fujimoto
Life of this patent
Estimating the term…
Abstract
A semiconductor memory has word lines, bit lines, memory cells configured to store signals by transition states of transistors and configured to provide the bit lines with the signals addressed by the word lines, a leak detecting line, leak generators configured to provide the leak detecting line with a leakage current and a signal compensator configured to detect a voltage state of the leak detecting line and to change the signals transmitted by the bit lines.
Claims11
A semiconductor memory comprising:
- a plurality of word lines;
- a plurality of bit lines arranged perpendicular to the word lines;
- a plurality of memory cells arranged in a matrix corresponding to a plurality of cross points of the word lines and the bit lines, and configured to store signals by transition states of transistors, and configured to provide the bit lines with the signals addressed by the word lines;
- a leak detecting line arranged parallel to the bit lines;
- a plurality of leak generators configured to provide the leak detecting line with a leakage current;
- and
- a signal compensator configured to detect a potential of the leak detecting line, and to change the signals transmitted by the bit lines.
4 more elements
Dependencies are inferred from the claim text.