Flash memory with shortened erasing operation time

Abstract

A flash memory having a nonvolatile memory cell, includes a plurality of banks each having a plurality of sectors, an erasing voltage generator circuit and a writing voltage generator circuit, wherein while an applying an erase pulse to a sector to be erased in a first bank, an erasing control is performed by, a pre-writing control is concurrently performed by applying a writing pulse to a sector to be erased in a second bank. At the time when erasing control of the sector to be erased in a first bank is finished, pre-writing control of the sector to be erased in a second bank is finished or partially finished, and thus the time required for erasing operations of the first and the second bank can be reduced.

Dependencies are inferred from the claim text.