Semiconductor memory and method of driving the same

A semiconductor memory comprising:

• a cell array including a plurality of memory cells each comprising:
• an electron trapping layer formed above a semiconductor substrate,
• a control gate formed above said electron trapping layer;
• a pair of a source and a drain formed in a surface region of said semiconductor substrate to sandwich a region below said control gate;
• and
• a control circuit for performing, during a sequence for writing data in a memory cell of said cell array, control including a detrap operation for setting said control gate at a negative voltage with respect to said semiconductor substrate, and at the same time setting said source and drain at 0 V or at a positive voltage or floating said source and drain;
• wherein
• the control circuit makes control such that the potential difference between the semiconductor substrate and the control gate upon the detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon the data erase operation.

A semiconductor memory comprising:

• a cell array including a plurality of memory cells each comprising:
• an electron trapping layer formed above a semiconductor substrate,
• a control gate formed above said electron trapping layer;
• and
• a pair of a source and a drain formed in a surface region of said semiconductor substrate to sandwich a region below said control gate;
• a control circuit for performing, when an operation performed in an erase sequence for erasing data in a memory cell of said cell array is different from the data erase operation, control including the detrap operation for setting said control gate at a negative voltage with respect to said semiconductor substrate, and at the same time setting said source and drain at 0 V or at a positive voltage or floating said source and drain;
• wherein
• a control circuit makes control such that the potential difference between the semiconductor substrate and the control gate upon a detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon a data erase operation.

A method of driving a semiconductor memory which comprises a cell array including a plurality of memory cells each comprising:

• an electron trapping layer formed above a semiconductor substrate,
• a control gate formed above the electron trapping layer;
• a pair of a source and a drain formed in a surface region of the semiconductor substrate to sandwich a region below the control gate,
• comprising a control process for performing control including:
• a data erase operation for setting the control gate of a memory cell of the cell array at a negative voltage with respect to the semiconductor substrate;
• and
• a detrap operation for making the absolute value of a negative voltage with respect to the semiconductor substrate, which is applied to the control gate, larger than that of the negative voltage during the data erase operation, and at the same time setting the source and drain at 0 V or at a positive voltage or floating the source and drain;
• wherein
• the control process makes control such that the potential difference between the semiconductor substrate and the control gate upon the detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon the data erase operation.

A method of driving a semiconductor memory which comprises a cell array including a plurality of memory cells each comprising:

• an electron trapping layer formed above a semiconductor substrate,
• a control gate formed above the election trapping layer;
• a pair of a source and a drain formed in a surface region of the semiconductor substrate to sandwich a region below the control gate,
• comprising a control process for performing, during a sequence for writing data in a memory cell of the cell array, control including a detrap operation for setting the control gate at a negative voltage with respect to the semiconductor substrate, and at the same time setting the source and drain at 0 V or at a positive voltage or floating the source and drain;
• wherein
• the control process makes control such that the potential difference between the semiconductor substrate and the control gate upon the detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon the data erase operation.

A method of driving a semiconductor memory which comprises a cell array including a plurality of memory cells each comprising:

• an electron trapping layer formed above a semiconductor substrate,
• a control gate formed above the electron trapping layer;
• and
• a pair of a source and a drain formed in a surface region of the semiconductor substrate to sandwich a region below the control gate;
• comprising a control process for performing, when an operation performed in an erase sequence for erasing data in the memory cell of the cell array is different from a data erase operation, control including a detrap operation for setting the control gate at a negative voltage with respect to the semiconductor substrate, and at the same time setting the source and drain at 0 V or at a positive voltage or floating the source and drain;
• wherein
• the control process makes control such that the potential difference between the semiconductor substrate and the control gate upon a detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon a data erase operation.