Semiconductor integrated circuit device with erasable and programmable fuse memory

A semiconductor integrated circuit device comprising:

• a fuse cell array;
• fuse cells arranged in the fuse cell array, the fuse cells including erasable and programmable nonvolatile memory cells;
• a fuse cell data program and erase circuit which programs fuse data to the erasable and programmable nonvolatile memory cells and erases the fuse data from the erasable and programmable nonvolatile memory cells;
• a fuse cell data control circuit which controls read out timing of the fuse data stored in the erasable and programmable nonvolatile memory cells, based on a first signal generated upon detection of power-on;
• and
• fuse data latch circuits which latch the fuse data read out from the erasable and programmable nonvolatile memory cells.