Programmable logic device circuit and method of fabricating same

A method of fabricating an integrated circuit, comprising:

• forming a plurality of nonvolatile transistors in a first area of the integrated circuit;
• forming a plurality of select transistors in a second area of the integrated circuit and a plurality of transistors in a third area;
• and
• forming electrical interconnections between nonvolatile transistors in the first area and select transistors in the second area so as to form a plurality of programmable logic device (PLD) cells, each of a plurality of PLD cells comprising a nonvolatile transistor connected in series with a distinct select transistor, to electrically connect transistors in the third area with each other to form combinatorial logic circuitry;
• and to electrically connect the PLD cells to transistors in the third area.

An integrated circuit, comprising:

• programmable logic device (PLD), comprising:
• a plurality of floating gate transistors disposed in at least one first area of a semiconductor substrate;
• a plurality of field effect transistors disposed in at least one second area of the semiconductor substrate;
• and
• a plurality of layers of electrically conductive material disposed over the semiconductor substrate and electrically connecting the floating gate transistors and the field effect transistors so as to form a plurality of PLD cells, each of the plurality of PLD cells comprising a floating gate transistor connected in series with at least one distinct field effect transistor, the plurality of PLD cells being connected between at least one source line and at least one bit line.

An integrated circuit, comprising:

• a plurality of floating gate transistors disposed in a first area of a semiconductor substrate;
• a plurality of field effect transistors disposed in a second area of the semiconductor substrate that is adjacent to the first area;
• and
• means for electrically connecting the plurality of floating gate transistors and the plurality of field effect transistors to form an array of programmable logic device (PLD) cells, each PLD cell comprising a selected one of the plurality of floating gate transistors from the first area and a selected field effect transistor from the second area.

A method of fabricating an integrated circuit, comprising:

• forming a plurality of nonvolatile transistors in a first area of the integrated circuit;
• forming a plurality of select transistors in a second area of the integrated circuit, wherein the second area is adjacent to the first area;
• and
• forming a plurality of programmable logic device (PLD) cells, each PLD cell formed by electrically interconnecting a selected one of the nonvolatile transistors from the first area with a selected one of the select transistors from the second area.

An integrated circuit, comprising:

• an array of PLD cells, each PLD cell comprised of a selected one of a plurality of nonvolatile transistors all located in a first area of a substrate and a selected one of a plurality of select transistors all located in a second area of the substrate adjacent the first area, each PLD cell being connected between a bit line and a source line:
• a plurality of sense amplifiers, each sense amplifier being coupled to a distinct source line;
• and
• an array of combinational logic having inputs coupled to the sense amplifiers and at least one output.