High density semiconductor memory cell and memory array using a single transistor
AssigneeKilopass Technologies, Inc.
InventorsJack Zezhong Peng, David Fong
Life of this patent
Estimating the term…
Abstract
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+region in the substrate underlying the gate of the transistor.
Claims11
A programmable memory cell useful in a memory array having column bitlines and row wordlines, the memory cell comprising:
- a transistor having a gate, a gate dielectric between the gate and over a substrate such that there is a stack comprising said gate, gate dielectric, and substrate, without any intervening conductive material, and first and second doped semiconductor regions formed in said substrate adjacent said gate and in a spaced apart relationship to define a channel region therebetween and under said gate, the gate being formed from one of said column bitlines;
- a row wordline segment coupled to the second doped semiconductor region of the transistor, said row wordline segment connected to one of said row wordlines;
- and
- a programmed doped region formed in said substrate in said channel region when said memory cell has been programmed.
A method of operating a programmable memory array comprising a plurality of row wordlines, a plurality of column bitlines, and a plurality of memory cells at respective crosspoints of the row lines and column lines, said memory cells comprising a transistor having a gate, a gate dielectric between the gate and over a substrate such that there is a stack comprising said gate, gate dielectric, and substrate, without any intervening conductive material, and first and second doped semiconductor regions formed in said substrate adjacent said gate and in a spaced apart relationship to define a channel region therebetween and under said gate, the gate being formed from one of said column bitlines, and a row wordline segment coupled to the second doped semiconductor region of the transistor, said row wordline segment connected to one of said row wordlines, the method comprising:
- applying a first voltage to a selected one of the column bitlines and gate of a selected transistor;
- and
- applying a second voltage to a selected one of the row wordlines;
- wherein the first voltage and the second voltage form a potential difference across the gate dielectric of said selected transistor to cause the formation of a programmed doped region in said substrate in said channel region of said selected transistor.
Dependencies are inferred from the claim text.