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US 6,856,529 B1Granted
Cutting CAM peak power by clock regioning
AssigneeMicron Technology, Inc.
InventorWilliam Radke
Life of this patent
Estimating the term…
Abstract
A CAM device architecture where CAM cells are divided into at least two arrays and each array is operated in a different clock domain so that at no time are the arrays simultaneously drawing maximum power. By dividing the CAM array into a plurality of arrays and staggering the search operation so that every array does not simultaneously draw maximum power, the peak power consumption of the CAM device is reduced.
Claims33
A content addressable memory (CAM) device, comprising:
- a plurality of CAM arrays, each having a plurality of CAM cells;
- a plurality of first priority encoders, each one of said first priority encoders being coupled to a respective one of said plurality of CAM arrays;
- at least one subsequent priority encoder coupled to said plurality of first priority encoders, said subsequent priority encoder receiving outputs from said plurality of first priority encoders and selecting one of said outputs;
- and
- a control circuit coupled to said plurality of CAM arrays, said plurality of first priority encoders, and said at least one subsequent priority encoder,
- wherein said control circuit operates said plurality of CAM arrays so that at least a first one of said plurality of CAM arrays is operated in accordance with a first clock domain and at least a second one of said plurality of CAM arrays is operated in accordance with a second different clock domain.
3 more elements
A processor based system, comprising:
- a processor;
- and
- a memory subsystem, coupled to said processor, said memory subsystem further comprising at least one content addressable memory (CAM) device, wherein at least one of said at least one CAM device further comprises,
- a plurality of CAM arrays, each having a plurality of CAM cells;
- a plurality of first priority encoders, each one of said first priority encoders being coupled to a respective one of said plurality of CAM arrays;
- at least one subsequent priority encoder coupled to said plurality of first priority encoders, said subsequent priority encoder receiving outputs from said plurality of first priority encoders and selecting one of said outputs;
- and
- a control circuit coupled to said plurality of CAM arrays, said plurality of first priority encoders, and said at least one subsequent priority encoder,
- wherein said control circuit operates said plurality of CAM arrays so that at least a first one of said plurality of CAM arrays is operated in accordance with a first clock domain and at least a second one of said plurality of CAM arrays is operated in accordance with a second different clock domain.
6 more elements
A method for operating a content addressable memory (CAM) device, comprising:
- controlling a search operation of at least a first CAM array in accordance with a first clock signal;
- and
- controlling a search operation of at least a second CAM array in accordance with a second clock signal,
- wherein said first and second clock signals are different.
1 more element
A router, comprising:
- a processor;
- a first network interface, coupled to said processor;
- a second network interface, coupled to said processor;
- and
- a memory subsystem, coupled to said processor, said memory subsystem further comprising at least one content addressable memory (CAM) device, wherein at least one of said at least one CAM device further comprises:
- a plurality of CAM arrays, each having a plurality of CAM cells;
- a plurality of first priority encoders, each one of said first priority encoders being coupled to a respective one of said plurality of CAM arrays;
- at least one subsequent priority encoder coupled to said plurality of first priority encoders, said subsequent priority encoder receiving outputs from said plurality of first priority encoders and selecting one of said outputs;
- and
- a control circuit coupled to said plurality of CAM arrays, said plurality of first priority encoders, and said at least one subsequent priority encoder,
- wherein said control circuit operates said plurality of CAM arrays so that at least a first one of said plurality of CAM arrays is operated in accordance with a first clock domain and at least a second one of said plurality of CAM arrays is operated in accordance with a second different clock domain;
- and
- wherein said processor searches a routing table stored in said memory subsystem to route packets between said first and second network interfaces.
10 more elements
Dependencies are inferred from the claim text.