Match line sensing amplifier for content addressable memory

A circuit for sensing a logic state of a match line of a content addressable memory (CAM) device, said circuit comprising:

• an input node coupled to said match line and adapted to receive a memory state logic signal;
• a precharge device switchingly coupled between said input node and a source of supply voltage;
• a first load device switchingly coupled between said input node and a second node;
• an input transistor having a gate and one of a source and a drain mutually coupled to said second node, and the other of said source and said drain coupled to a source of ground potential;
• an output transistor having one of a source and a drain coupled to said source of ground potential, a gate coupled to said second node and the other of said source and said drain coupled to an output node;
• and
• a sense-enable device coupled in series with a second load device between said source of supply voltage and said output node.

A hybrid current-voltage sensing circuit for sensing a match line of a content addressable memory (CAM) device comprising:

• at least one CAM cell coupled to said match line;
• a precharge circuit coupled to a supply voltage, said precharge circuit precharging a signal on said match line;
• a load circuit coupled to said match line for applying a load to said precharged match line signal;
• a mirror having a first portion and a second portion, said first portion coupled to said load circuit;
• and
• a sense enable circuit coupled to said supply voltage for enabling a sensing operation, said sense enable circuit coupled to said second portion of said mirror, said second portion of said mirror having an output corresponding to a state of said match line.

A content addressable memory (CAM) device comprising:

• at least one CAM cell coupled to a match line;
• a sensing circuit for sensing a logic state of said match line, said sensing circuit comprising:
• an input adapted to receive a first current signal, which changes based on a logic state of said match line;
• and
• a circuit having a first portion for receiving said first current signal and converting said first current signal to a first voltage signal and a second portion adapted to produce a second voltage output signal based on said first voltage signal and convert said second voltage signal into a third voltage signal.

A content addressable memory (CAM) device comprising:

• at least one CAM cell coupled to a match line;
• a sensing circuit for sensing a logic state of said match line, said sensing circuit comprising:
• an input node coupled to said match line and adapted to receive a memory state logic signal;
• a precharge device switchingly coupled between said input node and a source of supply voltage;
• a first load device switchingly coupled between said input node and a second node;
• an input transistor having a gate and one of a source and a drain mutually coupled to said second node, and the other of said source and said drain coupled to a source of ground potential;
• an output transistor having one of a source and a drain coupled to said source of ground potential, a gate coupled to said second node and the other of said source and said drain coupled to an output node;
• and
• a sense-enable device coupled in series with a second load device between said source of supply voltage and said output node.

A content addressable memory (CAM) device comprising:

• at least one CAM cell coupled to a match line;
• a sensing circuit for sensing a logic state of said match line, said sensing circuit comprising:
• a precharge circuit coupled to a supply voltage;
• a load circuit coupled to said match line;
• a current mirror having a first portion and a second portion, said first portion coupled to said load circuit;
• and
• a sense-enable circuit coupled to said supply voltage for enabling a sensing operation, said sense-enable circuit coupled to said second portion of said current mirror, said second portion of said current mirror having an output corresponding to a state of said match line.

A processing system comprising:

• a processor;
• a content addressable memory (CAM) device coupled to said processor via a bus, said CAM device comprising an apparatus for operating said CAM device, said apparatus further comprising:
• at least one CAM cell coupled to a match line;
• a sensing circuit for sensing a logic state of said match line, said sensing circuit comprising:
• an input adapted to receive a first current signal, which changes based on a logic state of said match line;
• and
• a circuit having a first portion for receiving said first current signal and converting said first current signal to a first voltage signal and a second portion adapted to produce a second voltage output signal based on said first voltage signal.

A processing system comprising:

• a processor;
• a content addressable memory (CAM) device coupled to said processor via a bus, said CAM device comprising an apparatus for operating said CAM device, said apparatus further comprising:
• at least one CAM cell coupled to a match line;
• a sensing circuit for sensing a logic state of said match line, said sensing circuit comprising:
• an input node coupled to said match line and adapted to receive a memory state logic signal;
• a precharge device switchingly coupled between said input node and a source of supply voltage;
• a first load device switchingly coupled between said input node and a second node;
• an input transistor having a gate and one of a source and a drain mutually coupled to said second node, and the other of said source and said drain coupled to a source of ground potential;
• an output transistor having one of a source and a drain coupled to said source of ground potential, a gate coupled to said second node and the other of said source and said drain coupled to an output node;
• and
• a sense-enable device coupled in series with a second load device between said source of supply voltage and said output node.

A processing system comprising:

• a processor;
• a content addressable memory (CAM) device coupled to said processor via a bus, said CAM device comprising an apparatus for operating said CAM device, said apparatus further comprising:
• at least one CAM cell coupled to a match line;
• a sensing circuit for sensing a logic state of said match line, said sensing circuit comprising:
• a precharge circuit coupled to a supply voltage;
• a load circuit coupled to said match line;
• a mirror having a first portion and a second portion, said first portion coupled to said load circuit;
• and
• a sense-enable circuit coupled to said supply voltage for enabling a sensing operation, said sense-enable circuit coupled to said second portion of said current mirror, said second portion of said current mirror having an output corresponding to a state of said match line.

A method for sensing a state of a memory circuit comprising:

• receiving a first current signal at an input node, said first current signal corresponding to a logic state of said memory circuit;
• converting said first current signal into a second voltage signal;
• and
• converting said second voltage signal into a third voltage signal.

A method of sensing a voltage to determine a state of a content accessible memory (CAM) device comprising:

• precharging said match line;
• applying a load to a match line;
• sensing a current affected by a logic state of said match line;
• producing a first voltage value;
• and
• producing and outputting a second voltage value from said first voltage value.