Phase-increase induced backporch decrease (PIBD) phase recovery method for video signal processing

A method to generate an optimum, phase shifted sampling clock for sampling a synchronized video signal A(t) having a synchronization signal SYNC pulse, said method comprising:

• generating a sampling clock having a first edge aligned with a trailing edge of said SYNC pulse wherein said sampling clock period comprises said SYNC pulse period divided by M;
• counting the number of sampling clock cycles N from said trailing edge of said SYNC pulse until said A(t) value at said first edge of said sampling clock exceeds a minimum value;
• thereafter phase shifting said sampling clock and said SYNC pulse forward until said A(t) value at said first edge of said sampling clock first exceeds a minimum value on clock cycle N−1 to thereby establish a worst case phase shift of said sampling clock;
• and
• thereafter sampling said A(t) at an offset from said worst case phase shift to thereby generate an optimum phase shifted sampling clock wherein said offset comprises a fraction of said sampling clock period.

An optimized phase shifted sampling clock circuit for sampling a synchronized video signal A(t) having a synchronization signal SYNC pulse, said circuit comprising:

• a means of generating a sampling clock having a first edge aligned with a trailing edge of said SYNC pulse wherein said sampling clock period comprises said SYNC pulse period divided by M;
• a means of counting the number of sampling clock cycles N from said trailing edge of said SYNC pulse until said A(t) value at said first edge of said sampling clock exceeds a minimum value;
• a means of phase shifting said sampling clock and said SYNC pulse forward until said A(t) value at said first edge of said sampling clock first exceeds a minimum value on clock cycle N−1 to thereby establish a worst case phase shift of said sampling clock;
• and
• a means of sampling said A(t) at an offset from said worst case phase shift to thereby generate an optimum phase shifted sampling clock.