Method and apparatus for controlling exposure of a CMOS sensor array

An apparatus for controlling a sensor array containing a first line of sensor cells arranged in a linear fashion, comprising:

• a first logic circuit for receiving a clock signal and to generate a first address, wherein said first logic circuit comprises an address generation circuit to provide said first address as a binary sequence whose value changes in response to each cycle of the clock signal and points to a line of sensor cells in the array, the binary sequence spans the entire sensor array in a single frame;
• a second logic circuit coupled to said first logic circuit to generate a line reset signal to said first line of sensor cells based on said first address;
• a third logic circuit coupled to said first logic circuit to receive said first address and to calculate a line read delay based on said first address and based on an offset value;
• and
• a fourth logic circuit coupled to said first logic circuit to generate a line read signal to said first line of sensor cells after said line read delay, to enable the sampling of a charge contained in each sensor cell in said first line of cells.

A method for controlling a CMOS sensor array containing a first CMOS sensor cell, comprising:

• receiving a clock signal and generating a first address;
• generating a reset signal to said first CMOS sensor cell based on said first address;
• calculating a read delay based on said first address and an offset value;
• and,
• generating a read address signal to said first CMOS sensor cell after said read delay.

An apparatus for controlling a CMOS sensor array containing a first CMOS sensor cell, comprising:

• a first logic circuit for receiving a clock signal and generating a first address;
• a second logic circuit coupled to said first logic circuit for receiving said first address and generating a reset signal to said first CMOS sensor cell based on said first address;
• a third logic circuit coupled to said first logic circuit for receiving said first address and calculating a read delay based on said first address and an offset value;
• and,
• a fourth logic circuit coupled to said first logic circuit for generating a read address signal to said first CMOS sensor cell after said read delay.

A method for controlling a CMOS sensor array containing a first CMOS sensor cell, comprising:

• receiving a first clock signal and in response storing a first address;
• generating a reset signal to said first CMOS sensor cell based on said first address;
• and then
• waiting a predetermined number of clock cycles;
• receiving a second clock signal and in response storing a second address;
• and,
• generating a read address signal to said first CMOS sensor cell based on said second address after said predetermined number of clock cycles.