Jitter-less phase detector in a clock recovery circuit

A jitter-less phase detector in a clock recovery circuit comprising:

• a first control signal generating circuit for generating a first control signal by inverting and delaying input data signals through half clock (0.5T), so that the first control signal has a pulse width starting from a transition of the data signal and lasting for half clock;
• a second control signal generating circuit for generating a high level second control signal when the data signal changes, so that the second control signal has a pulse width starting from a transition of the data signal and terminating at a falling edge of the clock;
• and
• a phase comparator for generating an up signal having a high-level from the falling edge of the first control signal to the falling edge of the second control signal when the falling edge of the first control signal is leading the falling edge of the second control signal, and generating a down signal having a high-level from the falling edge of the second control signal to the falling edge of the first control signal when the falling edge of the second control signal is leading the falling edge of the first control signal, so as to control a pair of current sources to selectively discharge and charge a capacitor.