Phase lock loop with controllable lock time
AssigneeSTMicroelectronics Pvt. Ltd.
InventorSaudas Dey
Life of this patent
Estimating the term…
Abstract
An improved phase locked loop (PLL) includes a frequency multiplier and a voltage controlled oscillator (VCO). The VCO includes a control circuit for automatically adjusting its initial free-running frequency in response to changes in an integer divider value. The adjusting is done so that the frequency difference between the initial free-running frequency divided by the integer divider value and a reference frequency is maintained at an approximately constant value. This results in a controllable lock time that is independent of the integer divider value.
Claims24
A phase locked loop (PLL) comprising:
- a programmable frequency divider network for dividing an input frequency by an integer value;
- and
- a frequency multiplier comprising a voltage controlled oscillator (VCO) and having a first input for receiving a reference frequency, a second input connected to an output of said programmable frequency divider network, and an output connected to an input of said programmable frequency divider network, said frequency multiplier generating at the output an output signal having a frequency equal to a product of the reference frequency and the integer value;
- said VCO comprising a control circuit for adjusting an initial free-running frequency of said VCO in response to changes in the integer value so that a frequency difference between the initial free-running frequency divided by the integer value and the reference frequency is maintained at an approximately constant value, resulting in a controllable lock time that is independent of the integer value.
A phase locked loop (PLL) comprising:
- a programmable frequency divider network for dividing an input frequency by an integer value;
- and
- a frequency multiplier comprising a voltage controlled oscillator (VCO) and having a first input for receiving a reference frequency, a second input connected to an output of said programmable frequency divider network, and an output connected to an input of said programmable frequency divider network, said frequency multiplier generating at the output an output signal having a frequency equal to a product of the reference frequency and the integer value;
- said vco comprising a ring oscillator comprising a plurality of voltage-controlled delay elements connectable in a loop, and an initial free-running frequency of said VCO being determined by a combined delay of said voltage-controlled delay elements connected in the loop, resulting in a controllable lock time that is independent of the integer value.
An integrated circuit comprising:
- a phase locked loop (PLL) comprising
- a programmable frequency divider network for dividing an input frequency by an integer value, and
- a frequency multiplier comprising a voltage controlled oscillator (VCO) and having a first input for receiving a reference frequency, a second input connected to an output of said programmable frequency divider network, and an output connected to an input of said programmable frequency divider network, said frequency multiplier generating at the output an output signal having a frequency equal to a product of the reference frequency and the integer value,
- said VCO comprising a control circuit for adjusting an initial free-running frequency of said VCO in response to changes in the integer value so that a frequency difference between the initial free-running frequency divided by the integer value and the reference frequency is maintained at an approximately constant value, resulting in a controllable lock time that is independent of the integer value.
A method for generating an output signal from a phase locked loop (PLL) comprising a programmable frequency divider network for dividing an input frequency by an integer value, and a frequency multiplier comprising a voltage controlled oscillator (VCO) having an output connected to an input of the programmable frequency divider network, the method comprising:
- providing a reference frequency to a first input of the frequency multiplier, and providing an output of the programmable frequency divider network to a second input of the frequency multiplier, and generating at the output of the frequency multiplier the output signal having a frequency equal to a product of the reference frequency and the integer value;
- and
- adjusting an initial free-running frequency of the VCO in response to changes in the integer value so that a frequency difference between the initial free-running frequency divided by the integer value and the reference frequency is maintained at an approximately constant value, resulting in a controllable lock time that is independent of the integer divider value.
Dependencies are inferred from the claim text.