Phase/frequency detector and phase lock loop circuit
AssigneeWolfson Microelectronics plc
InventorPaul Lesso
Life of this patent
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Abstract
The present invention relates to cycle slip detectors for phase and frequency detectors (PFD) and to lock detectors for phase lock loop (PLL) circuits. The present invention provides a cycle slip detector circuit for use with a phase and frequency detector circuit having first and second signal inputs, and arranged to provide first and second PLL control signal outputs responsive to clock edges in the first and second input signals respectively; the cycle slip detector circuit comprising: means for determining a cycle slip between said input signals by determining when a delayed output signal coincides with a respective input signal.
Claims22
A cycle slip detector circuit comprising:
- a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals;
- third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch input corresponding to said control signal output;
- delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.
A lock detector circuit for a phase lock loop having a phase and frequency detector;
- the lock detector comprising:
- a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals;
- third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output;
- delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means;
- and
- a circuit arranged to indicate lock when output signals indicating a cycle slip from the third or fourth latches have not been asserted for a predetermined time.
A phase or frequency mode indicator circuit for a phase lock loop, the circuit comprising:
- a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals;
- third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output;
- delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means;
- a circuit arranged to indicate a phase or frequency mode dependent on whether said cycle slip detector circuit indicates cycle slips.
A phase lock loop circuit comprising a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals;
- third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output;
- delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.
A phase lock loop circuit comprising a lock detector circuit comprising:
- a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals;
- third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output;
- delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means;
- a circuit arranged to indicate lock when output signals indicating a cycle slip from the third or fourth latches have not been asserted for a predetermined time.
A phase lock loop circuit comprising a phase of frequency mode indicator circuit comprising:
- a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals;
- third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output;
- delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means;
- a circuit arranged to indicate phase or frequency mode dependent on whether said cycle slip detector indicates cycle slips.
A clock frequency synthesiser comprising a phase lock loop circuit comprising a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals;
- third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output;
- delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.
Digital audio apparatus comprising a phase lock loop circuit comprising a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals;
- third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output;
- delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.
Dependencies are inferred from the claim text.