Clock divider circuit
AssigneeAgilent Technologies, Inc.
InventorTakashi Hidai
Life of this patent
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Abstract
A system that includes a first circuit configured generate a first set of encoded signals in response to a first clock signal and a second circuit configured to generate a second set of encoded signals in response to the first clock signal is provided. The system also includes a third circuit configured to generate a first pulse signal and a second pulse signal in response to the first set of encoded signals and the second set of encoded signals, and a fourth circuit configured to generate a second clock signal in response to the first pulse signal and the second pulse signal.
Claims25
A system comprising:
- a first circuit configured to receive a first clock signal and generate a first set of encoded signals in response to a positive edge of the first clock signal;
- a second circuit configured to receive the first clock signal and configured to generate a second set of encoded signals in response to a negative edge of the first clock signal;
- a third circuit configured to receive the first set of encoded signals and the second set of encoded signals and configured to generate a first pulse signal and a second pulse signal in response to the first set of encoded signals and the second set of encoded signals;
- and
- a fourth circuit configured to receive the first pulse signal and the second pulse signal, and configured to generate a second clock signal in response to the first pulse signal and the second pulse signal;
- wherein the first set of encoded signals and the second set of encoded signals each include n encoded signals, wherein the second clock signal has a frequency that is one divided by n of a frequency of the first clock signal, and wherein n is an integer greater than or equal to one.
A system comprising:
- a first means for generating a first set of encoded signals in response to a first clock signal;
- a second means for generating a second set of encoded signals in response to the first clock signal;
- a third means for generating first and second pulse signals in response to the first and second sets of encoded signals;
- and
- a fourth means for generating a second clock signal in response to the first and second pulse signals;
- wherein the second clock signal has a frequency that is one divided by n of a frequency of the first clock signal, and wherein n is an integer greater than or equal to one.
A method comprising:
- generating a plurality of sets of encoded signals using a first clock signal;
- generating a plurality of pulse signals using the plurality of sets of encoded signals;
- generating a second clock signal using the plurality of pulse signals;
- receiving a clock divide signal;
- and
- generating the second clock signal at a frequency associated with the clock divide signal.
Dependencies are inferred from the claim text.