Back to results
US 6,856,183 B2Granted
Scheme to improve performance of timing recovery systems for read channels in a disk drive
AssigneeAgere Systems Inc.
InventorViswanath Annampedu
Life of this patent
Estimating the term…
Abstract
A digital phase lock loop circuit including an error generation circuit for generating at least three error signals and a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals. By using at least three error signals, as opposed to just one, the drift in the sampling phase of the recovered clock is easily detected and corrected to reduce burst errors and to improve loss of lock (LOL) performance.
Claims27
A digital phase lock loop circuit for recovering a sampling clock comprising:
- an error generation circuit for generating at least three error signals from a sampled signal;
- and,
- a phase error adjustment circuit for generating at least first and second phase error adjustment signals from the at least three error signals for adjusting for at least an amount and direction of occurring phase drift, respectively, of a recovered sampling clock.
A read channel device comprising:
- an error generation circuit for generating at least three error signals from a sampled signal;
- and,
- a phase error adjustment circuit for generating at least first and second phase error adjustment signals from the at least three error signals for adjusting for at least an amount and direction of occurring phase drift, respectively, of a recovered sampling clock.
A data storage system comprising:
- a data storage assembly;
- a read channel device operable to read information stored on the data storage assembly, said read channel device comprising an error generation circuit for generating at least three error signals from a sampled signal;
- and, a phase error adjustment circuit for generating at least first and second phase error adjustment signals from the at least three error signals indicative of at least an amount and direction of occurring phase drift, respectively, of a recovered sampling clock.
A method for determining and correcting a phase error in a recovered sampling clock, comprising the steps of:
- generating at least three error signals from a sampled signal;
- and,
- generating at least first and second phase error adjustment signal from the at least three error signals for adjusting for at least an amount and direction of occurring phase drift, respectively, of said recovered sampling clock.
A digital phase lock loop circuit for recovering a sampling clock, comprising:
- an error generation circuit for generating at least three error signals from sampled signal sampled with said sampling clock, said at least three error signals comprising:
- at least one first error signal, said first error signal corresponding an error between a first sampled value from said sampled signal and a first ideal value for said sampled signal;
- at least one second error signal, said second error signal corresponding to an error between a second sampled value from said sampled signal, slightly ahead of the first sampled value in time, and the first ideal value;
- and
- at least one third error signal, said third error signal corresponding to an error between a third sampled value from said sampled signal, slightly behind the first sampled value in time, and the first ideal value;
- and
- a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals.
4 more elements
A digital phase Jock loop circuit for recovering a sampling clock, comprising:
- an error generation circuit for generating at least three error signals from sampled signal sampled with said sampling clock, said at least three error signals comprising:
- at least one first error signal, said first error signal corresponding to an error between a first sampled value from said sampled signal and a first ideal value for said sampled waveform;
- at least one second error signal, said second error signal corresponding to an error between a first interpolated sample value for said sampled signal, slightly ahead of the first sampled value in time, and the first ideal value;
- and,
- at least one third error signal, said third error signal corresponding to an error between a second interpolated sample value for said sampled signal, slightly behind the first sampled value in time, and the first ideal value;
- and
- a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals.
4 more elements
A digital phase lock loop circuit for recovering a sampling clock, comprising:
- an error generation circuit for generating at least three error signals from sampled signal sampled with said sampling clock, said at least three error signals comprising:
- at least one first error signal, said first error signal corresponding to an error between a first sampled value from said sampled signal and a first ideal value for said sampled signal;
- at least one second error signal, said second error signal corresponding to an error between the first sampled value and a second ideal value for said sampled signal which is slightly ahead of the first ideal value in time;
- and,
- at least one third error signal, said third error signal corresponding to an error between the first sampled value and a third ideal value for said sampled signal which is slightly behind the first ideal value in time;
- and
- a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals.
4 more elements
Dependencies are inferred from the claim text.