Programmable loop bandwidth in phase locked loop (PLL) circuit
AssigneeAltera Corporation
InventorsGregory W. Starr, Wanli Chang
Life of this patent
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Abstract
A PLL circuit is described. The PLL circuit includes: a feedback loop and a loop filter coupled to the feedback loop, where the loop filter is programmable to provide one of a plurality of bandwidths. In one embodiment, the loop filter is programmable to provide one of a plurality of resistances, each resistance of the plurality of resistances corresponding to one of the plurality of bandwidths. In one embodiment, the feedback loop includes a detector and a signal generator coupled to the detector.
Claims46
A phase locked loop circuit comprising:
- a feedback loop;
- and
- a loop filter coupled to the feedback loop, wherein the loop filter is programmable in user mode to provide one of a plurality of bandwidths.
A phase locked loop circuit comprising:
- a signal generator;
- and
- a loop filter coupled to the signal generator, wherein the loop filter is programmable in user mode to provide one of a plurality of bandwidths.
A method of providing an output clock signal, the method comprising:
- comparing a feedback clock signal with a reference clock signal;
- providing a control signal to a signal generator;
- selecting in user mode one of a plurality of bandwidths in a loop filter;
- and
- generating an output clock signal in response to the control signal.
Dependencies are inferred from the claim text.