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US 6,856,179 B2Granted
CMOS buffer with reduced ground bounce
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsRajesh Kaushik, Rajesh Narwal
Life of this patent
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Abstract
A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.
Claims17
An output buffer comprising:
- voltage terminals;
- an output stage including multiple, independently controllable output switches;
- an output driver stage providing a control signal for the output stage;
- and
- a correcting stage monitoring a voltage of at least one of the voltage terminals in view of the control signal, and dynamically controlling at least one of the controllable output switches so as to provide rapid response while limiting a voltage bounce at the voltage terminals within a predefined limit, the correcting stage including
- a first feedback switch connected between the output driver stage and the at least one controllable output switch,
- an inverter connected between the at least one voltage terminal and a control terminal of the first feedback switch, the inverter having a trip point controlled by the voltage on the at least one voltage terminal, and
- a second feedback switch connected between the at least one voltage terminal and the at least one controllable output switch.
5 more elements
An output buffer comprising:
- voltage terminals;
- an output stage including a plurality of independently controllable switching transistors having output terminals connected together;
- an output driver stage providing a control signal for the output stage;
- and
- a correcting stage monitoring a voltage of at least one of the voltage terminals, and controlling at least one of the controllable switching transistors to limit a voltage bounce at the voltage terminals within a predefined limit, the correcting stage including
- a first feedback switch connected between the output driver stage and the at least one controllable switching transistor,
- an inverter connected between the at least one voltage terminal and a control terminal of the first feedback switch, the inverter having a trip point controlled by the voltage on the at least one voltage terminal, and
- a second feedback switch connected between the at least one voltage terminal and the at least one controllable switching transistor.
5 more elements
A method for reducing voltage bounce while maintaining speed of operation of an output buffer comprising:
- providing multiple, independently controllable output switches in an output stage of the output buffer;
- providing a control signal to the output stage from an output driver stage;
- and
- monitoring a voltage of at least one terminal, with a correcting stage, whenever the control signal changes state and dynamically controlling at least one of the controllable output switches so as to provide rapid response while limiting a voltage bounce at the at least one terminal within a predefined limit, the correcting stage including
- a first feedback switch connected between the output driver stage and the at least one controllable output switch,
- an inverter connected between the at least one voltage terminal and a control terminal of the first feedback switch, the inverter having a trip point controlled by the voltage on the at least one voltage terminal, and
- a second feedback switch connected between the at least one voltage terminal and the at least one controllable output switch.
4 more elements
A method for reducing voltage bounce while maintaining speed of operation of an output buffer comprising:
- providing a plurality of independently controllable switching transistors having output terminals connected together in an output stage of the output buffer;
- providing a control signal for the output stage;
- and
- monitoring a voltage of at least one terminal, with a correcting stage, whenever the central signal changes state and dynamically controlling at least one of the controllable switching transistors to limit voltage bounce at the at least one terminal within a predefined limit, the correcting stage including
- a first feedback switch receiving the control signal and connected to the at least one controllable switching transistor,
- an inverter connected between the at least one voltage terminal and a control terminal of the first feedback switch, the inverter having a trip point controlled by the voltage on the at least one voltage terminal, and
- a second feedback switch connected between the at least one voltage terminal and the at least one controllable switching transistor.
4 more elements
Dependencies are inferred from the claim text.