Sequential logic circuit for frequency division

A circuit comprising:

• a shift register having a state of N−1 Boolean values Q<i>, i=1, 2, . . . , N−1, wherein in response to a clock signal the state changes so that Q<i−1>is shifted into Q<i> for i=2, . . . , N−1;
• a set-reset flip-flop comprising a SET input port having a voltage to represent a Boolean value S and a RESET input port having a voltage to represent a Boolean value R, the set-reset flip-flop to provide an output voltage representative of a Boolean value Q<0>, wherein in response to the clock signal Q<0> is a Boolean 1 when S is a Boolean 1 and Q<0> is a Boolean 0 when R is a Boolean 1, and wherein Q<0> does not change in response to the clock signal when both S and R are a Boolean 0, wherein in response to the clock signal Q<0> is shifted into Q<1>;
• and
• logic to provide at the RESET input port a voltage representative of the Boolean value {Q<L−1><Q<L−2> . . . Q<0>} where is a Boolean AND and L is a positive integer not greater than N.

A circuit comprising:

• a shift register having a state of N−1 Boolean values Q<i>, i=1, 2, . . . , N−1, wherein in response to a clock signal the state changes so that Q<i−1>is shifted into Q<i> for i=2, . . . , N−1;
• a set-reset flip-flop comprising a SET input port having a voltage to represent a Boolean value S and a RESET input port having a voltage to represent a Boolean value R, the set-reset flip-flop to provide an output voltage representative of a Boolean value Q<0>, wherein in response to the clock signal Q<0> is a Boolean 1 when S is a Boolean 1 and Q<0> is a Boolean 0 when R is a Boolean 1, and wherein Q<0> does not change in response to the clock signal when both S and R are a Boolean 0, wherein in response to the clock signal Q<0> is shifted into Q<1>;
• and
• logic to provide at the SET input port a voltage representative of the Boolean value {Q#<M−1><Q#<M−2> . . . Q#<0>}, where is a Boolean AND, Q#<i> is the Boolean complement of Q<i>, and M is a positive integer not greater than N.

A system comprising:

• a clock circuit to provide a clock signal, the clock signal having a first transition and a second transition in each clock cycle;
• a shift register having a state of N−1 Boolean values Q<i>, i=1, 2, . . . , N−1, wherein on each of the first transitions of the clock signal the state changes so that Q<i−1> is shifted into Q<i> for i=2, . . . , N−1;
• a set-reset flip-flop comprising a SET input port, a RESET input port, a clock input port to receive the clock signal, and to provide an output voltage representative of a Boolean value Q<0> on each of the first transitions of the clock signal so that Q<0> is shifted into Q<1>;
• and
• logic to provide at the RESET input port a voltage representative of the Boolean value {Q<L−1><Q<L−2> . . . Q<0>} where is a Boolean AND and L is a positive integer not greater than N.

A system comprising:

• a clock circuit to provide a clock signal, the clock signal having a first transition and a second transition in each clock cycle;
• a shift register having a state of N−1 Boolean values Q<i>, i=1, 2, . . . , N−1, wherein on each of the first transitions of the clock signal the state changes so that Q<i−1> is shifted into Q<i> for i=2, . . . , N−1;
• a set-reset flip-flop comprising a SET input port, a RESET input port, a clock input port to receive the clock signal, and to provide an output voltage representative of a Boolean value Q<0> on each of the first transitions of the clock signal so that Q<0> is shifted into Q<1>;
• and
• logic to further provide at the SET input port a voltage representative of the Boolean value {Q#<M−1><Q#<M−2> . . . Q<0>}, where is a Boolean AND, Q#<i> is the Boolean complement of Q<i>, and M is a positive integer not greater than N.

A circuit to divide down the frequency of an input clock signal, the circuit comprising:

• a shift register;
• a set-reset flip-flop comprising a set input port, a reset input port, and an output port coupled to the shift register;
• and
• combinational logic to provide feedback from the shift register and the set-reset flip-flop to at least one of the set or reset input ports.