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US 6,856,171 B1Granted
Synchronization of programmable multiplexers and demultiplexers
AssigneeLattice Semiconductor Corporation
InventorFulong Zhang
Life of this patent
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Abstract
Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output circuitry. In accordance with another embodiment, a clock divider along with an edge clock distribution scheme is employed to distribute clock and reset signals for input/output circuitry.
Claims13
A programmable logic device comprising:
- a clock divider circuit adapted to receive a first clock signal and a first reset signal and provide a second reset signal synchronized to the first clock signal;
- a plurality of input/output circuits each adapted to receive the second reset signal and the first clock signal and synchronize the second reset signal to the first clock signal to generate a local synchronization signal, wherein the local synchronization signal in each of the plurality of input/output circuits is synchronized to a clock cycle of the first clock signal;
- a first distribution path for the first clock signal, the first distribution path couplable between the clock divider circuit and the plurality of input/output circuits;
- and
- a second distribution path for the second reset signal, the second distribution path couplable between the clock divider circuit and the plurality of input/output circuits.
2 more elements
A method of synchronizing a plurality of input/output circuits on a programmable logic device, the method comprising:
- receiving a first reset signal and a first clock signal;
- generating a second reset signal synchronized to the first clock signal;
- transmitting the first clock signal and the second reset signal through a first distribution path and a second distribution path, respectively, to the plurality of input/output circuits;
- and
- synchronizing the second reset signal to the first clock signal at each of the plurality of input/output circuits to generate a local synchronization signal.
2 more elements
Dependencies are inferred from the claim text.