Clock signal transmission circuit
AssigneeRenesas Technology Corp.
InventorNiichi Itoh
Life of this patent
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Abstract
A clock generator (10a) outputs either a first clock signal or a second clock signal. The second clock signal is higher in frequency than the first clock signal. Under control of a control signal (CNTL1), when the first clock signal and the second clock signal are outputted from the clock generator (10a), a selector (81a) transmits the first and second clock signals to a clock transmission line (42) and to a clock transmission line (41), respectively. The clock transmission line (41) is greater in linewidth than the clock transmission line (42). Under control of the control signal (CNTL1), a selector (82a) connects either the clock transmission line (41) or the clock transmission line (42) to the outside.
Claims10
A clock signal transmission circuit selectively receiving a first clock signal and a second clock signal, said first clock signal having a first frequency and said second clock signal having a second frequency higher than said first frequency, said clock signal transmission circuit comprising:
- a first clock transmission line for carrying said first clock signal;
- and
- a second clock transmission line for carrying said second clock signal, said second clock transmission line being greater in linewidth than said first clock transmission line, wherein
- no transmission of said second clock signal occurs through said first clock transmission line, and
- no transmission of said first clock signal occurs through said second clock transmission line.
Dependencies are inferred from the claim text.