Field programmable gate array with a variably wide word width memory
AssigneeIrvine Sensors Corporation
InventorsVolkan H. Ozguz, Randolph S. Carlson, Keith D. Gann, John P. Leon
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Abstract
A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as mXN where m is the number of word width bits per memory chip and N is the number of memory chips.
Claims34
A combined memory array and field programmable gate array device comprising:
- a field programmable gate array (FPGA);
- an access lead network electrically coupled and proximate to the FPGA;
- and
- a plurality of external memories electrically coupled and proximate to the access lead network;
- wherein the FPGA can independently access each of the plurality of external memories via the access lead network without use of an address/data bus.
A method of combining a memory array with a field programmable gate array comprising the steps of:
- providing a field programmable gate array (FPGA);
- disposing the FPGA on a surface of an interposer board and electrically coupling the FPGA thereto;
- and
- disposing a plurality of external memories on a surface of the interposer board and electrically coupling the plurality of external memories thereto;
- wherein the FPGA is independently coupled to each of the plurality of external memories via an access lead network without use of an address/data bus.
A field programmable gate array having a stacked memory array comprising:
- an interposer board having access leads;
- a field programmable gate array (FPGA) mounted on a side of the interposer board and electrically coupled to the access leads;
- and
- at least two external memories electrically coupled to the access leads and stacked on a side of the interposer board,
- wherein the FPGA can independently access each of the at least two external memories via the access leads.
A method of combining memory array and field programmable gate array system comprising the steps of:
- providing a field programmable gate array (FPGA);
- providing an access lead network electrically coupled and proximate to the FPGA;
- and
- providing a plurality of external memories electrically coupled and proximate to the access lead network;
- wherein the FPGA can independently access each of the plurality of external memories via the access lead network without use of an address/data bus.
A combined system of a memory array with a field programmable gate array comprising:
- a field programmable gate array (FPGA);
- the FPGA on a surface of an interposer board and electrically coupling the FPGA thereto;
- and
- a plurality of external memories on a surface of the interposer board and electrically coupling thereto;
- wherein the FPGA can independently access each of the plurality of external memories via an access lead network without use of a bus.
Dependencies are inferred from the claim text.