Method and program product for evaluating a circuit

A method for identifying a worst case voltage drop node in an integrated circuit, the circuit comprising at least a plurality of wires, a plurality of transistors, and a plurality of power supplies, the method comprising the steps of:

• creating a resistor model of the design by dividing each of the wires into a plurality of wire segments, each wire segment being defined by a substantially straight run of a constant width, determining the resistance of each of said wire segments by multiplying its sheet resistivity by a ratio of its length to width, representing each of said wire segments in said resistor model with a wire resistor of a resistance substantially equal to said wire segment resistance, representing each of the plurality of transistors in said resistor model with a switch resistor having a resistance substantially equal to the resistance of the respective of the transistors, providing a plurality of simulated DC power supplies connected to said resistor model at locations that correspond to the location of DC power supplies in the circuit, said resistor model defining a plurality of nodes comprising at least power nodes and internal nodes, said power nodes being separated from one of said simulated DC power supplies by only one or more wire resistors;
• and
• performing a DC power analysis on said resistor model by simulating supply of DC power from said plurality of simulated DC power supplies to said resistor model, determining the voltage drop at each of said power nodes, and determining a worst-case node having the largest voltage drop.

A computer program product for identifying a worst case impedance caused voltage drop node in an integrated circuit design, the circuit comprising a plurality of wires, a plurality of transistors, and a plurality of power supplies, the program product comprising computer executable instructions embedded in a computer readable medium that when executed by the computer cause the computer to:

• create a resistor network model by extracting circuit topology data from a data repository, said topology data comprising at least wire geometry data, wire sheet resistivity data, transistor geometry data, using said topology data to sub-divide each of the plurality of wires into a plurality of wire segments, each of said segments comprising a substantially straight run of a substantially constant width, determine the resistance of each of said wire segments by considering the sheet resistivity, length, and width of said wire segment, represent each of said wire segments in said resistor model as a wire resistor, said wire resistor having a resistance substantially equal to said wire segment resistance, determine the resistance of each of the plurality of transistors by considering at least said transistor geometry data, represent each of the plurality of transistors with a switch resistor having a resistance substantially equal to respective of the transistors, said resistor network model comprising a plurality of nodes between said resistors, said nodes comprising power nodes and internal nodes;
• perform a DC power analysis on said resistor network model by simulating a plurality of DC power supplies connected to said resistor network at power nodes corresponding to power supply locations on the network design;
• and measure a voltage drop at each of said power nodes, compare said voltage drops to determine a worst case node having the largest voltage drop.

A method for evaluating a power distribution network for an integrated circuit, the circuit comprising at least a plurality of wires, a plurality of switches, and a plurality of power supplies, the method comprising the steps of:

• creating a circuit model of the circuit by representing each of the plurality of wires with at least a wire element, representing each of the plurality of switches with a switch element, said circuit model defining a plurality of nodes between connected elements;
• performing a DC circuit analysis on said circuit model by simulating supply of DC power from the plurality of power supplies to said circuit model, and determining the voltage drop at at least a portion of said plurality of nodes of said circuit model;
• and
• determining a worst-case node having a larger voltage drop than any others of said nodes.

A computer program product for evaluating the quality of a power distribution network of an integrated circuit design, the circuit comprising a plurality of wires, a plurality of transistors, and a plurality of power supplies, the program product comprising computer executable instructions embedded in a computer readable medium that when executed by the computer cause the computer to:

• create a circuit model by representing the plurality of wires with wire elements and representing the plurality of transistors with switch elements, said circuit model comprising a plurality of nodes between said elements, said nodes comprising power nodes and internal nodes;
• perform a DC circuit analysis on said circuit model by simulating a plurality of DC power supplies connected to said circuit model at locations corresponding to power supply locations on the network design, and measure a voltage drop at each of said power nodes;
• and,
• comparing said voltage drops measured at said power nodes to determine a worst case voltage node having the largest voltage drop.