US 6,856,120 B2 · Regulator circuit

Abstract

A regulator circuit capable of reducing an increase in an output voltage during a sudden drop in a load current without increasing the power consumption during a steady state. When a current in load IL1 changes suddenly from a large current to a minute current during a steady state, electric charges are charged in capacitor CL1 due to a response delay of the negative feedback control, and an output voltage becomes higher than a target voltage. Then, voltage of node N34 drops, diode 31 gets turned off, and a voltage is held in capacitor 32. As a result, output of comparator 42 changes from a low level to a high level, and n-type MOS transistor 82 gets turned on. In addition, when the voltage between the gate and the source of n-type MOS transistor 50 becomes lower than the voltage of voltage source 71 due to a drop in the voltage of node N34, comparator 72 is also reverted to the high level.

Claims5

Dependent claims

A regulator circuit having

a voltage output circuit which provides a voltage in accordance with voltage level of a control signal input,
a peak hold circuit which holds the peak level of the control signal on the polarity side where the output voltage is increased at a prescribed attenuation rate, and
a load control circuit which compares the level of the control signal with the peak level held by the peak hold circuit and changes the load impedance of the voltage output circuit in accordance with the result of said comparison.

Dependencies are inferred from the claim text.

Regulator circuit

Life of this patent

Regulator circuit

Life of this patent

Abstract

Claims5