Semiconductor latches and SRAM devices

A method of forming a semiconductor latch for integrated circuits, said latch adapted to receive a first supply voltage and a second supply voltage substantially at a lower voltage level than said first supply voltage, the method comprised of:

• fabricating a first inverter with logic transistors utilizing a first semiconductor layer, said first inverter fabrication comprising:
• fabricating a first and a second conducting path of the first inverter in said first semiconductor layer, said first conducting path coupled between said first supply voltage and an output, said second conducting path coupled between said second supply voltage and said output;
• depositing the logic transistor gate-dielectric layer on said first semiconductor layer;
• depositing the logic transistor gate-poly silicon layer on said logic gate dielectric layer;
• and
• fabricating gate regions in said gate-poly layer above a portion of said first and second conducting paths;
• and
• depositing an isolation layer above said first inverter;
• and
• fabricating a second inverter with thin film transistors (TFT) above the logic transistors utilizing
• a second semiconductor layer, said second inverter fabrication comprising:
• depositing the second semiconductor layer on said isolation layer, substantially above said first semiconductor layer;
• fabricating a first and a second conducting path of the second inverter in said second semiconductor layer, said first conducting path coupled between said first supply voltage and an output, said second conducting path coupled between said second supply voltage and said output;
• depositing the TFT gate-dielectric layer on said second semiconductor layer;
• depositing the TFT gate-poly silicon layer on said TFT gate-dielectric layer;
• and
• fabricating gate regions above a portion of said first and second conducting paths.

A method of forming a semiconductor latch for integrated circuits, said latch adapted to receive a first supply voltage and a second supply voltage substantially at a lower voltage level than said first supply voltage, the method comprising:

• depositing an isolation layer above a first module layers said first module comprising a high mobility semiconductor substrate layer used to fabricate logic transistors;
• and
• depositing a semiconductor thin film layer;
• and
• fabricating a first and a second conducting path of a first inverter in said semiconductor thin film layer, said first conducting path coupled between said first supply voltage and a first output, said second conducting path coupled between said second supply voltage and said first output;
• and
• fabricating a first and a second conducting path of a second inverter in said semiconductor thin film layer, said first conducting path coupled between said first supply voltage and a second output, said second conducting path coupled between said second supply voltage and said second output.