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US 6,856,027 B2Granted
Multi-chips stacked package
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorMeng-Jen Wang
Life of this patent
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Abstract
A multi-chips stacked package at least comprises a substrate, an upper chip, a lower chip, a plurality of electrically conductive wires and a plurality of conductive bumps. The upper chip is flip-chip bonded to the upper surface of the substrate; and the lower chip is accommodated in the opening and wire-bonded to the upper chip. Furthermore, the lower chip can be wire-bonded to the substrate via a plurality of another electrically conductive wires, which directly connect the lower chip and the substrate.
Claims14
A multi-chips stacked package, comprising:
- a substrate having an upper surface, a lower surface and an opening passing through the upper surface and the lower surface;
- an upper chip having a first active surface and a first back surface wherein the upper chip is flipped over and attached to the upper surface of the substrate via a plurality of electrically conductive bumps;
- and
- a lower chip accommodated in the opening, disposed on the first active surface of the upper chip and electrically connected to the first active surface of the upper chip through a plurality of first electrically conductive wires.
1 more element
Dependencies are inferred from the claim text.