US 6,856,025 B2Granted

Chip and wafer integration process using vertical connections

AssigneeInternational Business Machines Corporation

InventorsH. Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan

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Abstract

A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Claims4

Dependent claims

A semiconductor structure comprising:

a substrate having a top surface and a bottom surface and a via extending through the substrate;
a first electrical conductor formed in the via;
a first layer overlying the top surface of the substrate, the first layer including a first conducting pad on a top surface of the layer and a second electrical conductor connecting the first conducting pad and the first electrical conductor;
a second conducting pad on the bottom surface of the substrate electrically connected to the first electrical conductor, so that the first conducting pad and the second conducting pad are electrically connected;
a second layer overlying the first layer and having a via formed therein exposing the first conducting pad;
and
a plate having a stud formed thereon, the plate overlying the second layer so that the stud is aligned to the via and makes electrical contact with the first conducting pad.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/465,506Filed 19 Jun 2003 · division
Priority: 19 Dec 2001
Published: US 2003/0111733 A120 Nov 2003
Granted: 15 Feb 2005
Term ends: Not estimatedThe source records don’t support an estimate.

Classification25 codes

H10W 72/20
Interconnections or connectors in packages: bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0245
The interconnections being through-semiconductor vias: comprising use of blind vias during the manufacture

Family

Application10/026,103Parent of this division · filed 19 Dec 2001
US 2003/0215984 A1Pre-grant publication · published 20 Nov 2003
US 6,599,778 B2Parent of this division
US 2003/0111733 A1Published application
US 6,856,025 B2This patent

From the US filing history. Foreign family members aren’t listed.