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US 6,856,000 B2Granted
Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies
AssigneeTexas Instruments Incorporated
InventorsJoe R. Trogolo, William Loftin, William F. Kyser, Jr.
Life of this patent
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Abstract
An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
Claims3
An integrated circuit, comprising:
- a semiconductor substrate with an upper surface;
- a n-type collector region contained in said semiconductor substrate;
- a p-type collector region contained in said semiconductor substrate and separated from said n-type collector region;
- a p-type base region contained in said n-type collector region;
- a n-type base region contained in said p-type collector region;
- a n-type emitter region with an upper surface contained in said p-type base region;
- a p-type emitter region with an upper surface contained in said n-type base region;
- a first interfacial oxide layer with an upper surface formed on said upper surface of said n-type emitter region;
- a second interfacial oxide layer with an upper surface formed on said upper surface of said p-type emitter region;
- a p-type polysilicon emitter layer formed on said upper surface of said second interfacial oxide layer wherein said p-type polysilicon emitter layer does not contain fluorine;
- and
- a n-type polysilicon emitter layer formed on said upper surface of said first interfacial oxide layer wherein said n-type polysilicon emitter layer contains fluorine.
9 more elements
Dependencies are inferred from the claim text.