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US 6,855,995 B2Granted
Physically defined varactor in a CMOS process
AssigneeIntel Corporation
InventorMichael W. Altmann
Life of this patent
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Abstract
A differential varactor is physically defined in a CMOS process using a using the diffusion mask of a polycide gate rather than a P (+) mask, as is commonly used. The differential CMOS varactor may be used in a phase locked loop (PLL) of a voltage-controlled oscillator (VCO) to enable a transceiver to communicate at OC-3/STM-1 data rates using SONET/SDH signaling formats.
Claims19
An apparatus, comprising:
- two rectangular diffusions of P (+) material disposed in an n-well formed in a p-substrate using a complementary metal oxide semiconductor (CMOS) process;
- a polycide gate disposed between the two rectangular diffusions of P (+) material;
- and
- a pair of inductors disposed on the substrate,
- the two rectangular diffusions of P (+) material and the pair of inductors being coupled in a voltage-controlled oscillator (VCO) configuration.
2 more elements
An apparatus, comprising:
- two rectangular diffusions of P (+) material disposed in an n-well diffused into a p-substrate;
- and
- a polycide gate disposed between the two rectangular diffusions of P (+) material in a complementary metal oxide semiconductor (CMOS) process;
- and
- a lightly doped drain (LDD) disposed between the two rectangular diffusions of P (+) material, the two rectangular diffusions of P(+) material to extend under at least one edge of the polycide gate.
2 more elements
An apparatus, comprising:
- two rectangular diffusions of P (+) material disposed in an n-well diffused into a p-substrate;
- and
- a polycide gate disposed between the two rectangular diffusions of P (+) material in a complementary metal oxide semiconductor (CMOS) process;
- and
- a halo implant disposed between the two rectangular diffusions of P (+) material, the two rectangular diffusions of P(+) material to extend under at least one edge of the polycide gate.
2 more elements
A system, comprising:
- a voltage variable capacitor having two rectangular diffusions of P (+) material disposed in an n-well diffused into a p-substrate and a polycide gate disposed between the two rectangular diffusions of P (+) material in a complementary metal oxide semiconductor (CMOS) process;
- a pair of inductors formed on the substrate in the CMOS process and coupled to the voltage variable capacitor in a voltage-controlled oscillator (VCO) configuration;
- and
- a clock divider coupled to an output of the VCO.
1 more element
A system, comprising:
- a transceiver having a first phase lock-locked loop and a second phase lock-locked loop, each phase lock-locked loop having:
- a voltage variable capacitor, the voltage variable capacitor comprising two rectangular diffusions of P (+) material disposed in an n-well diffused into a p-substrate and a polycide gate disposed between the two rectangular diffusions of P (+) material in a complementary metal oxide semiconductor (CMOS) process;
- and
- a pair of inductors formed on the substrate in the CMOS process and coupled to the voltage variable capacitor in a voltage-controlled oscillator (VCO) configuration;
- and
- a coaxial transformer coupled to the transceiver.
3 more elements
Dependencies are inferred from the claim text.