Damascene finfet gate with selective metal interdiffusion

A method of forming a multiple voltage threshold fin field effect transistor (FinFET), comprising:

• forming a fin;
• forming a source region adjacent a first end of the fin and a drain region adjacent a second end of the fin;
• forming a dummy gate comprising a first material in a first pattern over the fin;
• forming a dielectric layer adjacent sides of the dummy gate;
• removing the first material to form a trench in the dielectric layer corresponding to the first pattern;
• forming a first metal gate layer in the trench, wherein the first metal gate layer comprises a first metal material;
• and
• forming a second metal gate layer in the trench adjacent the first metal gate layer, wherein the second metal gate layer comprises a second metal material and wherein the second metal material selectively diffuses through the first metal material via metal interdiffusion to produce a multiple voltage threshold FinFET.

A method of forming a fin field effect transistor comprising a fin and a source region adjacent a first end of the fin and a drain region adjacent a second end of the fin, the method comprising:

• forming a dummy oxide layer over the fin;
• depositing a layer of first material over the fin and dummy oxide layer;
• etching the layer of the first material to form a dummy gate in a first pattern;
• depositing a dielectric layer over the dummy gate and source and drain regions;
• planarizing the dielectric layer to expose a top surface of the dummy gate;
• removing the first material to form a trench in the dielectric layer corresponding to the first pattern;
• forming a gate insulation layer in the trench;
• forming a first gate layer in the trench, the first gate layer comprising a first metal material, wherein the first metal material comprises a first work function;
• and
• forming a second gate layer in the trench, the second gate layer comprising a second metal material, wherein the second metal material comprises a second work function.