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US 6,855,985 B2Granted
Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
AssigneesAdvanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
InventorsRichard K. Williams, Michael E. Cornell, Wai Tien Chan
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Abstract
A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
Claims162
A family of semiconductor devices formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said family including CMOS transistors, bipolar transistors and DMOS transistors, isolated from the substrate by an isolation structure,
- said isolation structure comprising:
- an N-type isolation region extending downward from a surface of said substrate, said N-type isolation region comprising a deep N layer and an annular first N well enclosing an isolated P region of said P-type substrate;
- said family comprising:
- a CMOS pair, said CMOS pair comprising a PMOS and an NMOS,
- said PMOS comprising:
- a second N well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions underlying a field oxide layer, said relatively deep central portion underlying a first opening in said field oxide layer;
- a first gate separated from said substrate by a first gate oxide layer;
- a P-type source region located at the surface of said substrate on one side of said first gate;
- and
- a P-type drain region located at the surface of said substrate on an opposite said of said first gate from said P-type source region;
- said NMOS comprising:
- a first P well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions underlying the field oxide layer, said relatively deep central portion underlying a second opening in said field oxide layer;
- a second gate separated from said substrate by a second gate oxide layer;
- an N-type source region located at the surface of said substrate on one side of said second gate;
- and
- an N-type drain region located at the surface of said substrate on an opposite said of said second gate from said N-type source region;
- and
- a lateral N-channel DMOS transistor comprising:
- a trench formed at a surface of said substrate, a conductive gate material being disposed in said trench, said gate material being separated from said semiconductor substrate by a dielectric layer;
- an N-type source region adjacent a side wall of said trench and said surface of said substrate;
- a P body region touching and beneath said source region and adjacent to said side wall of said trench, said source and body regions being electrically connected;
- an N-type drain region adjacent said surface of said substrate and spaced apart laterally from said source and body regions, said drain region having a first doping concentration of N-type impurity;
- and
- an N-type drift region abutting said body and drain regions and said side wall of said trench, said drift region comprising a second doping concentration of N-type impurity, said drift region comprising a deeper portion under said body region and a shallower portion under a field oxide layer
- wherein said first doping concentration is greater than said second doping concentration;
- and
- an NPN bipolar transistor enclosed by said isolation structure, said isolation structure electrically isolating said NPN bipolar transistor from said P substrate and forming a collector of said NPN bipolar transistor, said NPN bipolar transistor comprising:
- an second P well located at said surface of said substrate within said isolated region, said second P well and said isolated region forming the base of said NPN bipolar transistor and
- an N-type region located at said surface of said substrate within said P well, said N-type region forming the emitter of said NPN bipolar transistor.
26 more elements
A family of semiconductor devices formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said family comprising:
- a CMOS pair, said CMOS pair comprising a PMOS and a NMOS, said PMOS comprising:
- an N well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions underlying a field oxide layer, said relatively deep central portion underlying a first opening in said field oxide layer;
- a first gate separated from said substrate by a first gate oxide layer;
- a P-type source region located at the surface of said substrate on one side of said first gate;
- and
- a P-type drain region located at the surface of said substrate on an opposite said of said first gate from said P-type source region;
- said NMOS comprising:
- a P well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions underlying the field oxide layer, said relatively deep central portion underlying a second opening in said field oxide layer, said P well having said breakdown voltage;
- a second gate separated from said substrate by a second gate oxide layer;
- an N-type source region located at the surface of said substrate on one side of said second gate;
- and
- an N-type drain region located at the surface of said substrate on an opposite said of said second gate from said N-type source region;
- an isolation structure comprising an N-type isolation region extending downward from a surface of said substrate, said N-type isolation region comprising a deep N layer and an annular second N well enclosing an isolated P region of said P-type substrate, wherein said isolation structure contains said NMOS and said PMOS;
- and
- a lateral DMOS transistor comprising:
- a trench formed at a surface of said substrate, a conductive gate material being disposed in said trench, said gate material being separated from said semiconductor substrate by a dielectric layer;
- an N-type source region adjacent a side wall of said trench and said surface of said substrate;
- a P body region touching and beneath said source region and adjacent to side wall of said trench, said source and body regions being electrically connected;
- an N-type drain region adjacent said surface of said substrate and spaced apart laterally from said source and body regions, said drain region having a first doping concentration of N-type impurity;
- and
- an N-type drift region abutting said body and drain regions and said side wall of said trench, said drift region comprising a second doping concentration of N-type impurity, said drift region comprising a deeper portion under said body region and a shallower portion under a field oxide layer, wherein said first doping concentration is greater than said second doping concentration.
18 more elements
A family of semiconductor devices formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said family of semiconductor devices including an NPN bipolar transistor, a CMOS, and a DMOS, said NPN bipolar transistor, said CMOS and said DMOS being isolated from the substrate by an isolation structure;
- said isolation structure comprising an N-type isolation region extending downward from a surface of said substrate, said N-type isolation region comprising a deep N layer and an annular first N well enclosing an isolated P region of said P-type substrate:
- a first PMOS comprising:
- a second N well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions underlying a field oxide layer, said relatively deep central portion underlying a first opening in said field oxide layer;
- a first gate separated from said substrate by a first gate oxide layer;
- a P-type source region located at the surface of said substrate on one side of said first gate;
- and
- a P-type drain region located at the surface of said substrate on an opposite said of said first gate from said P-type source region;
- a second PMOS comprising:
- a third N well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions underlying a field oxide layer, said relatively deep central portion underlying a first opening in said field oxide layer;
- said third N well having a different doping profile than said second N well
- a second gate separated from said substrate by a second gate oxide layer;
- a P-type source region located at the surface of said substrate on one side of said second gate;
- and
- a P-type drain region located at the surface of said substrate on an opposite said of said second gate from said P-type source region;
- a first NMOS comprising:
- a first P well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions underlying the field oxide layer, said relatively deep central portion underlying a second opening in said field oxide layer;
- a third gate separated from said substrate by a third gate oxide layer;
- an N-type source region located at the surface of said substrate on one side of said third gate;
- and
- an N-type drain region located at the surface of said substrate on an opposite
- said of said third gate from said N-type source region;
- and
- a second NMOS comprising:
- a second P well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions underlying the field oxide layer, said relatively deep central portion underlying a second opening in said field oxide layer;
- a fourth gate separated from said substrate by a fourth gate oxide layer;
- an N-type source region located at the surface of said substrate on one side of said fourth gate;
- an N-type drain region located at the surface of said substrate on an opposite said of said fourth gate from said N-type source region, said second P well having a different doping profile than said second N well;
- a lateral DMOS transistor comprising:
- a trench formed at a surface of said substrate, a conductive gate material being disposed in said trench, said gate material being separated from said semiconductor substrate by a dielectric layer;
- an N-type source region adjacent a side wall of said trench and said surface of said substrate;
- a P body region touching and beneath said source region and adjacent to said side wall of said trench, said source and body regions being electrically connected;
- an N-type drain region adjacent said surface of said substrate and spaced apart laterally from said source and body regions, said drain region having a first doping concentration of N-type impurity;
- and
- an N-type drift region abutting said body and drain regions and said side wall of said trench, said drift region comprising a second doping concentration of N-type impurity, said drift region comprising a deeper portion under said body region and a shallower portion under a field oxide layer, wherein said first doping concentration is greater than said second doping concentration;
- and
- an NPN transistor comprising:
- a first said isolation structure enclosing said NPN bipolar transistor, electrically isolating said NPN from said P substrate into first isolated P region and forming the collector of said NPN transistor;
- a third P well located at said surface of said substrate within said first isolated region, said third P well and said first isolated P region forming the base of said NPN transistor and
- a second N-type region located at said surface of said substrate within said third P well, said second N-type region forming the emitter of said NPN transistor.
36 more elements
Dependencies are inferred from the claim text.