Back to results
US 6,855,984 B1Granted
Process to reduce gate edge drain leakage in semiconductor devices
AssigneeTexas Instruments Incorporated
InventorsZhiqiang Wu, Shaoping Tang, Song Zhao
Life of this patent
Estimating the term…
Abstract
The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted n-type dopants counteract portions of strongly p-type HALO or pocket regions creating a smoother dopant profile or transition from a portion of the active regions to the channel. However, the blanket implant is performed at a relatively low energy so as to not significantly alter one or more other portions of the active regions to other portions of the device.
Claims9
A semiconductor device comprising:
- a first active region formed within a well;
- a second active region formed within the well;
- a channel region defined between the first active region and the second active region;
- and
- a first active region interface having a center portion defining an interface from the first active region to the channel region and having a lower portion defining an interface from the first active region to a lower portion of the well, wherein the center portion of the active region interface provides a relatively smooth dopant transition from the first active region to the channel region.
2 more elements
Dependencies are inferred from the claim text.