Self aligned double gate transistor having a strained channel region and process therefor
AssigneeAdvanced Micro Devices, Inc.
InventorsQi Xiang, James N. Pan, Ming Ren Lin
Life of this patent
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Abstract
A method of manufacturing an integrated circuit with a strained semiconductor channel region. The method can provide a double gate structure. The gate structure can be provided in and above a trench. The trench can be formed in a compound semiconductor material such as a silicon-germanium material. The strained semiconductor can increase the charge mobility associated with the transistor. A silicon-on-insulator substrate can be used.
Claims20
A method of manufacturing an integrated circuit on a substrate including a compound semiconductor layer, the method comprising:
- providing a trench in the compound semiconductor layer;
- providing a bottom gate in the trench;
- and
- forming a strained semiconductor above the bottom gate and in the trench.
A transistor comprising:
- a first gate conductor disposed in a trench of a compound semiconductor layer;
- a strained semiconductor layer disposed in the trench and above the first gate conductor;
- and
- a second gate conductor disposed above the strained semiconductor layer and above the trench.
A process of forming a transistor having a strained silicon channel region, the process comprising:
- forming a trench in a compound semiconductor material;
- forming a first gate at a bottom portion of the trench;
- growing strained silicon above the first gate for the strained silicon channel region;
- and
- forming a second gate above the strained silicon.
Dependencies are inferred from the claim text.