Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling

An array of electrically programmable and erasable memory devices comprising:

• a substrate of semiconductor material of a first conductivity type;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
• and
• each of the active regions including a column of pairs of memory cells extending in the first direction, each of the memory cell pairs including:
• a first region and a pair of second regions spaced apart in the substrate and having a second conductivity type, with channel regions formed in the substrate between the first region and the second regions,
• a pair of electrically conductive floating gates each disposed vertically over and insulated from portion of on of the channel regions and a portion of the first region,
• an electrically conductive source region electrically connected to the first region in the substrate, the source region having a lower portion that is disposed vertically over the first region and laterally adjacent to and insulated from the pair of floating gates, and an upper portion that extends up and over the floating gates and terminates in a pair of first ends that each is disposed vertically over and insulated from one of the floating gates,
• a pair of electrically conductive control gates each having a first portion and a second portion, wherein for each of the control gates, the first control gate portion is disposed laterally adjacent to and insulated from one of the floating gates and the second control gate portion extends up and over the one floating gate and terminates in a second end that is disposed vertically over and insulated from the one floating gate;
• wherein each of the first ends is disposed laterally adjacent to and insulated from one of the second ends such that no portion of the control gates is disposed directly between the floating gates and the source region, and
• an insulation material disposed directly between the floating gates and the second ends, and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough.