Thin film transistor, fabrication method thereof and liquid crystal display having the thin film transistor

A thin film transistor comprising:

• a gate electrode formed on a substrate;
• a gate insulating film formed on the gate electrode;
• an operational semiconductor film formed on the gate insulating film on the gate electrode;
• a channel protection film formed on the operational semiconductor film;
• a source electrode and a drain electrode formed, respectively, on each side of a top surface of the channel protection film and being connected to the operational semiconductor film;
• and
• the channel protection film including a first insulating layer that contacts an upper surface of the operational semiconductor film and a second insulating layer formed on the first insulating layer,
• wherein a dielectric constant of the second insulating layer is less than or equal to the dielectric constant of the first insulating layer;
• a thickness of the first insulating layer is within the range of approximately 100-300 nm, and a thickness of the second insulating layer is greater than or equal to the thickness of the first insulating layer;
• and
• a width of the second insulating layer is less than a width of said first insulating layer, such that light doping drain (LDD) areas can be formed on the operational semiconductor film.

A method of fabricating a bottom gate type thin film transistor comprising:

• forming a gate electrode on a substrate;
• forming a gate insulating film on the gate electrode;
• forming an operational semiconductor film on the gate insulating film on the gate electrode;
• forming a channel protection film on the operational semiconductor film, wherein the channel protection film is formed by laminating a first insulating layer to contact an upper surface of the operational semiconductor film and by laminating a second insulating layer on the first insulating layer;
• reducing the parasitic capacitance formed by the channel protection film by:
• selecting materials for the first and second insulating layers such that said second insulating layer has a dielectric constant that is less than or equal to the dielectric constant of the first insulating layer;
• selecting the thickness of the first insulating layer to be within the range of approximately 100-300 nm, and selecting the thickness of the second insulating layer to be is greater than or equal to the thickness of the first insulating layer;
• forming a source electrode and a drain electrode on each side, respectively, of a top surface of the channel protection film, and connecting said source and drain electrodes to the operational semiconductor film;
• and
• making the second insulating layer of a narrower width than the first insulating layer and forming light doping drain (LDD) areas on the operational semiconductor film by using the second insulating layer as a shield.

An active matrix type liquid crystal display comprising:

• a plurality of gate wirings formed on a substrate;
• a plurality of data wirings arranged perpendicular to the gate wirings;
• and
• a thin film transistor formed for each of a plurality of pixel areas defined by the plurality of gate wirings and the plurality of data wirings,
• wherein the thin film transistor includes a gate electrode formed on a substrate, a gate insulating film formed on the gate electrode, an operational semiconductor film formed on the gate insulating film on the gate electrode, a channel protection film formed on the operational semiconductor film, and a source electrode and a drain electrode formed, respectively, on each side of a top surface of the channel protection film and being connected to the operational semiconductor film, and
• wherein the channel protection film includes a first insulating layer contacting an upper surface of the operational semiconductor film and a second insulating layer formed on the first insulating layer
• a dielectric constant of the second insulating layer is less than or equal to the dielectric constant of the first insulating layer;
• a thickness of the first insulating layer is within the range of approximately 100-300 nm, and a thickness of the second insulating layer is greater than or equal to the thickness of the first insulating layer;
• and
• the second insulating layer is less than a width of the first insulating layer, such that light doping drain (LDD) areas can be formed on the operational semiconductor film.

A bottom gate type thin film transistor comprising:

• a gate electrode formed on a substrate;
• a gate insulating film formed on the gate electrode;
• an operational semiconductor film formed on the gate insulating film on the gate electrode;
• a channel protection film formed on the operational semiconductor film;
• a source electrode and a drain electrode formed, respectively, on each side of a top surface of the channel protection film and being connected to the operational semiconductor film;
• and
• the channel protection film including a first insulating layer that contacts an upper surface of the operational semiconductor film and a second insulating layer formed on the first insulating layer;
• wherein a thickness of the first insulating layer is within the range of approximately 100-300 nm, and a thickness of the second insulating layer is greater than or equal to the thickness of the first insulating layer;
• and
• a width of the second insulating layer is less than a width of the first insulating layer, such that light doping drain (LDD) areas can be formed on the operational semiconductor film.