CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsHyuk-Ju Ryu, Young-Wug Kim, Chang-Bong Oh, Hee-Sung Kang
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Abstract
In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.
Claims21
A method of fabricating a semiconductor device, comprising:
- forming a gate oxide layer on a semiconductor substrate, a device isolation region being formed on the substrate to define an NMOS region and a PMOS region;
- sequentially forming a silicon germanium layer and an amorphous conductive layer on the gate oxide layer;
- removing the amorphous conductive layer and the silicon germanium layer in the NMOS region;
- forming a polysilicon layer in the NMOS and PMOS regions;
- and
- patterning the polysilicon layer in the NMOS region until the gate insulating layer is exposed and patterning the polysilicon layer, the amorphous conductive layer and the silicon germanium layer in the PMOS region until the gate insulating layer is exposed to form gate electrodes in the NMOS and PMOS regions.
A method of fabricating a semiconductor device, comprising:
- forming a gate oxide layer on a semiconductor substrate, a device isolation region being formed on the substrate to define an NMOS region and a PMOS region;
- forming a lower polysilicon electrode seeding layer on the gate oxide layer;
- forming a silicon germanium electrode layer on the lower polysilicon electrode seeding layer;
- forming an amorphous electrode layer on the silicon germanium electrode layer;
- forming a mask pattern on the amorphous electrode layer in the PMOS region so as to expose the NMOS region;
- dry-etching the amorphous electrode layer an a portion of the underlying silicon germanium electrode layer in the NMOS region exposed by the mask pattern;
- removing the mask pattern;
- selectively wet-etching a residue of the silicon germanium electrode layer exposed by the dry etch down to a top surface of the lower polysilicon electrode seeding layer in the NMOS region;
- forming an upper polysilicon electrode layer on the lower polysilicon electrode seeding layer in the NMOS region and the silicon germanium electrode layer in the PMOS region, respectively;
- and
- patterning the stacked electrode layers to form gate electrodes in the NMOS and PMOS regions, respectively.
Dependencies are inferred from the claim text.