Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance

A method of fabricating a planar architecture charge trapping dielectric memory cell circuit with square gate memory cells, the method comprising:

• fabricating an oxide layer on a surface of a substrate;
• fabricating a charge trapping dielectric over the tunnel dielectric;
• fabricating a mask over the charge trapping dielectric to define and mask a core region and define and expose a periphery region;
• etching the charge trapping dielectric to remove the charge trapping dielectric in the periphery region to expose the oxide layer;
• fabricating a gate oxide layer in the periphery region by growing additional oxide on the oxide layer in the periphery region;
• simultaneously depositing a polysilicon layer over the charge trapping dielectric in the core region and over the gate oxide layer in the periphery region;
• applying a word line mask over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between within the core region and to mask the periphery region;
• etching the polysilicon layer to expose the charge trapping dielectric in the trench regions;
• applying a bit line mask over the polysilicon layer to mask “gates” in a second direction perpendicular to the first direction and to expose bit line regions there between within the core region and to mask gates and expose source/drain regions within the periphery;
• etching the polysilicon layer and the charge trapping dielectric layer to expose the tunnel dielectric layer in the bit line regions and to expose the gate oxide in the source/drain regions;
• fabricating insulating spacers on exposed sidewalls of the polysilicon layer and the charge trapping layer in both the core region and the periphery region;
• simultaneously removing the tunnel dielectric layer to expose the substrate between insulating spacers in the bit line regions and removing the gate oxide layer to expose the substrate in the source/drain regions;
• fabricating a conductor on the exposed substrate in the bit line regions and in the source/drain regions;
• and
• fabricating word line conductors that electrically couple remaining portions of the polysilicon layer along word lines in the first direction.