DRAM cell
AssigneeSamsung Electronics Co., Ltd.
InventorsChul-Ho Shin, Kyeong-Koo Chi
Life of this patent
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Abstract
A method of manufacturing a DRAM cell includes forming an isolation layer on a given region of a substrate to define an active region having a plurality of line shaped sub-regions; forming at least a pair of cell transistors in each line shaped sub-region, each cell transistor of a pair having a common drain region and respective source regions; forming a bit line pad on each common drain region and a storage node pad on each source region; forming a bit line pad protecting layer pattern having portions parallel to the word line, that covers the bit line pad; and forming storage nodes on storage node pads. The storage nodes of the DRAM cell contact with the storage node pads and are insulated electrically from the bit line pad by the bit pad protecting layer pattern.
Claims8
A method of manufacturing a DRAM cell comprising:
- forming an isolation layer on a region of a substrate to define an active region of the substrate, the active region having line shaped sub-regions;
- forming a word line pattern having pairs of line shaped portions on and crossing the active region;
- forming impurity regions in the active region by impurity implantation,
- the impurity regions including common drain regions respectively disposed between line shaped portions opposite of the pairs of line shaped portions of the word line pattern in the line shaped sub-regions of the active region, and source regions respectively disposed on both sides of the line shaped portions opposite the common drain regions in the line shaped sub-regions;
- forming word line spacers on side walls of the word line pattern;
- forming bit line pads and storage note pads respectively on the common drain regions and the source regions;
- forming a bit line pad protecting layer pattern, having line shaped portions disposed in parallel with the pairs of line shaped portions of the word line pattern, that covers the bit line pads;
- and
- forming storage nodes in direct contact on the storage node pads and electrically insulated from the bit line pads by the bit line pad protecting layer pattern.
Dependencies are inferred from the claim text.