US 6,855,590 B2Granted

Method of manufacturing the semiconductor device intended to prevent a leakage current from occuring due to a gate induced drain leakage effect

AssigneeSamsung Electronics Co., Ltd.

InventorsSang-Hun Seo, Seung-Hyun Park, Han-Sin Lee, Moo-Sung Kim, Won-Suk Yang

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Abstract

A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

Claims11

Dependent claims

A semiconductor device manufacturing method comprising the steps of:

forming a first dielectric film on an entire upper part of a semiconductor substrate;
forming a photoresist pattern on a p-well including a gate pattern of an NMOS transistor and a gate spacer thereof, and subsequently implanting ions into an n-well for forming a high concentration source/drain regions of a PMOS by using the first dielectric film formed on upper parts of a gate pattern and a gate spacer of a PMOS transistor as an implant mask;
and
forming an interlayer dielectric film thereon and then forming a contact,
wherein said semiconductor substrate includes a PMOS transistor region in the n-well;
an NMOS transistor region in the p-well;
the gate pattern of the PMOS transistor formed on the PMOS transistor region and the gate spacers formed on both side walls of the gate pattern thereof, and the gate pattern of the NMOS transistor formed on the NMOS transistor region and the gate spacers formed on both side walls of the gate pattern thereof;
the n-well having a low concentration source/drain regions formed by ion-implantation using the gate pattern of the PMOS transistor as an implant mask;
and the p-well having a low concentration source/drain regions formed by ion-implantation using the gate pattern of the NMOS transistor as an implant mask and a high concentration source/drain regions formed by ion-implantation using the gate pattern and the gate spacers of the NMOS transistor as an implant mask.

6 more elements

A semiconductor device manufacturing method comprising the steps of:

forming a metal film on upper parts of a gate pattern of a PMOS transistor and a gate pattern of an NMOS transistor on a semiconductor substrate, and then forming a capping layer entirely over the semiconductor substrate including the gate patterns and gate spacers of the NMOS and PMOS transistors for performing a silicidation process and forming a silicide film on the upper parts of the gate patterns of the PMOS and NMOS transistors;
forming a photoresist pattern on a p-well including the gate pattern of the NMOS transistor and a gate spacer, and subsequently implanting ions into an n-well for forming a high concentration source/drain regions by using as an implant mask the capping layer formed on the upper parts of the gate pattern and a gate spacer of the PMOS transistor;
and
forming an interlayer dielectric film thereon and then forming a contact,
wherein said semiconductor substrate includes a PMOS transistor region in the n-well;
an NMOS transistor region in the p-well;
the gate pattern of the PMOS transistor formed on the PMOS transistor region and the gate spacers formed on both side walls of the gate pattern thereof, and the gate pattern of the NMOS transistor formed on the NMOS transistor region and the gate spacers formed on both side walls of the gate pattern thereof;
the n-well having a low concentration source/drain regions formed by ion-implantation using the gate pattern of the PMOS transistor as an implant mask;
and the p-well having a low concentration source/drain regions formed by ion-implantation using the gate pattern of the NMOS transistor as an implant mask and a high concentration source/drain regions formed by ion-implantation using the gate pattern and the gate spacers of the NMOS transistor as an implant mask.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/650,089Filed 28 Aug 2003
Priority: KR 2002-5132229 Aug 2002
Published: US 2004/0144981 A129 Jul 2004
Granted: 15 Feb 2005
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10P 30/204
Characterised by the semiconductor materials: into Group IV semiconductors
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions