US 6,850,449 B2 · Semiconductor memory device having mode storing one bit data in two memory cells and method of controlling same

Abstract

A device has a bit line pair including first and second bit lines, a sense amplifier commonly connected to the bit line pair, and first and second cells connected at intersecting portions of first and second word lines and the first and second bit lines. In a normal mode, the first and second word lines are assigned separate addresses, whereas in a partial mode, the first and second word lines are assigned the same address. The first and second cells complimentarily store one bit of data. In storing a data in a first cell of two cells comprised in a twin cell into a second cell when set to the partial mode, the second word line is activated based on a trigger signal generated by a refresh timer during a precharge period for the bit line pair, and subsequently the precharge is completed. The first word line is then activated based on a delayed signal of the trigger signal, and the sense amplifier is activated to amplify a differential voltage between the bit line pair, so that the data of the first cell is written back into the first and second cells.

Claims21

Dependent claims

A semiconductor memory device, comprising:

a sense amplifier;
first and second word lines;
first and second bit lines coupled to said sense amplifier;
a first memory cell coupled to said first word line and said first bit line;
and
a second memory cell coupled to said second word line and said second bit line;
wherein, in a normal mode, the first and second word lines are assigned separate addresses from each other, and data access operation is performed in the first and second memory cells separately;
whereas in a partial mode, the first and second word lines are assigned the same address to maintain one bit data in the first and second memory cells;
wherein, in order to copy a data in the first memory cell into the second memory cell, based on a switching from the normal mode to the partial mode,
the second word line is activated in a precharge period for the first and second bit lines, so that a precharge voltage is written into the second memory cell;
then, the first word line is activated;
and
then, the sense amplifier is activated to amplify a differential voltage between the first and second bit lines to store said data stored in said first memory cell into said second memory cell.

10 more elements

A semiconductor memory device, comprising:

a sense amplifier;
first and second word lines;
first and second bit lines coupled to said sense amplifier;
a first memory cell coupled to said first word line and said first bit line;
and
a second memory cell coupled to said second word line and said second bit line;
wherein, in a normal mode, the first and second word lines are assigned separate addresses from each other, and data access operation is performed in the first and second memory cells separately;
whereas in a partial mode, the first and second word lines are assigned the same address to maintain one bit data in the first and second memory cells;
and
wherein, in order to copy a data in the first memory cell into the second memory cell, based on a switching from the normal mode to the partial mode,
the first word line is activated;
then, the sense amplifier is activated to amplify a differential voltage between the first and second bit lines;
and
the second word line is activated, thereby storing said data stored in said first memory cell into said second memory cell;
when said copying is operated, said first word line is activated at a first activate period, said second word line is activated at a second active period which is shorter than said first active period.

12 more elements

A method of controlling a semiconductor memory device that stores and holds one bit of data complementarily by two memory cells respectively connected to two bit lines, which form a bit line pair, commonly connected to one sense amplifier, the method comprising the steps of:

resetting, when copying a cell data of one of the two memory cells into the other one of the memory cells, a cell data of the other one of the memory cells that is a copy destination;
and
activating, after resetting the other one of the memory cells, a word line connected to the one of the memory cells, amplifying by the sense amplifier the data of the one of the memory cells to be output to the bit line pair, and storing the cell data of the one of the memory cells into the other one of the memory cells from the sense amplifier via the bit line pair.

Dependencies are inferred from the claim text.

Semiconductor memory device having mode storing one bit data in two memory cells and method of controlling same

Life of this patent

Semiconductor memory device having mode storing one bit data in two memory cells and method of controlling same

Life of this patent

Abstract

Claims21