Information handling system featuring a BJT-based bi-directional level translator
AssigneeDell Products L.P.
InventorsJoseph D. Mallory, Nikolai V. Vyssotski
Life of this patent
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Abstract
A method of implementing bi-directional level translation in an information handling system includes coupling a first device port via a first resistor to a first voltage. A second device port is coupled via a second resistor to a second voltage different from the first voltage. Lastly, a single bipolar junction transistor (BJT) couples the first device port to the second device port, the single bipolar junction transistor including an emitter coupled to the first device port, a base coupled via a third resistor to the first voltage, and a collector coupled to the second device port, wherein the bipolar junction transistor operates as a bi-directional level translator between the first and second device ports.
Claims19
A method of implementing bi-directional level translation in an information handling system, said method comprising:
- coupling a first device port to the system via a first resistor to a first voltage;
- coupling a second device port to the system via a second resistor to a second voltage different from the first voltage;
- coupling the first device port to the second device port via a single bipolar junction transistor (BJT), the single bipolar junction transistor includes an emitter coupled to the first device port, a base coupled via a third resistor to the first voltage, and a collector coupled to the second device port, wherein the bipolar junction transistor operates as a bi-directional level translator between the first and second device ports;
- and
- selecting the first resistor and the second resistor values based upon load impedances and load capacitances, as well as, rise times required on the first device port and the second device port, wherein the third resistor value is selected as a function of the emitter current, VCC1, Vbc, Vil_max on the second port, and Vol_max on the first device port and a reverse Beta of the BJT at the lowest operational temperature.
An information handling system implementing bi-directional level translation comprising:
- a microprocessor;
- a storage coupled to the microprocessor;
- a plurality of ports coupled to the system;
- a first device port couple via a first resistor to a first voltage;
- a second second device port coupled via a second resistor to a second voltage different from the first voltage;
- and
- a single bipolar junction transistor (BJT) coupling the first device port to the second device port, said single bipolar junction transistor including an emitter coupled to the first device port, a base coupled via a third resistor to the first voltage, and a collector coupled to the second device port, wherein said bipolar junction transistor operates as a bi-directional level translator between the first and second device ports, wherein the first and second resistor values are selected based upon load impedances and load capacitances, as well as, rise times required on said first device port and said second device port and wherein the third resistor value is selected as a function of the emitter current, VCC1, Vbc, Vil_max on said second port, and Vol_max on said first device port and a reverse Beta of the BJT at the lowest operational temperature.
A computer system comprising:
- a microprocessor;
- a storage coupled to the microprocessor;
- a display coupled to the system;
- a plurality of ports coupled to the system;
- a first device port coupled via a first resistor to a first voltage;
- a second second device port coupled via a second resistor to a second voltage different from the first voltage;
- a single bipolar junction transistor (BJT) coupling the first device port to the second device port, said single bipolar junction transistor including an emitter coupled to the first device port, a base coupled via a third resistor to the first voltage, and a collector coupled to the second device port, wherein said bipolar junction transistor operates as a bi-directional level translator between the first and second device ports;
- and
- selecting the first resistor and the second resistor values based upon load impedances and load capacitances, as well as, rise times required on the first device port and the second device port, wherein the third resistor value is selected as a function of the emitter current, VCC1, Vbc, Vil_max on the second port, and Vol_max on the first device port and a reverse Beta of the BJT at the lowest operational temperature.
Dependencies are inferred from the claim text.