Wafer-level package for micro-electro-mechanical systems
AssigneeInstitute of Microelectronics
InventorsRanganathan Nagarajan, Chirayarikathuveedu Sankarapillai Premachandran, Yu Chen, Vaidyanathan Kripesh
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Abstract
A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.
Claims18
A method for forming wafers having through-wafer vias for forming interconnects for wafer-level packaging of devices, the method comprising the steps of:
- depositing metal on one of two wafers;
- bonding the two wafers using the metal deposited on the one of the two wafers;
- forming a through-wafer via in one of the two wafers;
- filling the through-wafer via with a conductive material;
- and
- forming a cavity in the one of the two wafers having the through-wafer via, wherein the cavity is superposable over a device, wherein the conductive material first fills by one of electroplating and electroless plating the through-wafer via at the side of the one of the two wafers having the through-wafer via to which the other of the one of the two wafers is bondable.
A method for forming wafers having through-wafer vias for forming interconnects for wafer-level packaging of devices, the method comprising the steps of:
- depositing metal on one of two wafers;
- bonding the two wafers using the metal deposited on the one of the two wafers;
- forming a through-wafer via in one of the two wafers;
- and
- filling the through-wafer via with a conductive material wherein the conductive material first fills by one of electroplating and electroless plating the through-wafer via at the side of the one of the two wafers having the through-wafer via to which the other of the one of the two wafers is bondable.
Dependencies are inferred from the claim text.