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US 6,842,816 B1Granted
Configurable glueless microprocessor interface
AssigneeNetwork Elements, Inc.
InventorDonald R. Primrose
Life of this patent
Estimating the term…
Abstract
A host control interface for use in interfacing an external host processor with internal control/status registers of an integrated circuit is provided. In accordance with the teachings of the present invention, the control interface selectively couples the integrated circuit with an interchangeable one of a variety of host processor types. In one embodiment, the control interface supports processors having a multiplexed address/data port as well as processors having separate address and data ports. Similarly, in one embodiment, the control interface supports processors utilizing a transfer start indication signal in cooperation with a read/write signal, as well as processors utilizing separate read/write strobes.
Claims24
An integrated circuit comprising:
- switching logic;
- and
- a control interface having:
- a first interface for connection to an interchangeable one of a first bus of a first processor, and a first and second bus of a second processor,
- a second interface for connection to a data bus and an address bus of said switching logic, and
- selection logic coupled to said first and second interfaces and equipped to receive a control signal identifying one of a first control mode to couple said first bus of said first processor to both said data bus and said address bus of said switching logic, and a second control mode to couple said first bus of said second processor to said data bus of said switching logic and to couple said second bus of said second processor to said address bus of said switching logic.
3 more elements
An integrated circuit comprising:
- switching logic:
- and
- a control interface having:
- a first interface for connection to an interchangeable one of a first bus of a first processor, and a first and second bus of a second processor,
- a second interface for connection to a data bus and an address bus of said switching logic,
- selection logic coupled to said first and second interfaces and equipped to receive a control signal identifying one of a first control mode to couple said first bus of said first processor to both said data bus and said address bus of said switching logic, and a second control mode to couple said first bus of said second processor to said data bus of said switching logic and to couple said second bus of said second processor to said address bus of said switching logic, and
- delay circuitry to programmably delay transmission of an address from one of said first and second processors to said address bus of said switching logic.
4 more elements
A control interface for transmitting signals between an integrated circuit and an identifiable one of at least a first processor type operating in accordance with a first protocol and a second processor type operating in accordance with a second protocol, comprising:
- a first signal path to couple one of a first bus of said first processor type and a second bus of said second processor type, with a data bus of said integrated circuit based at least in part upon an identified processor type;
- a second signal path to couple said first bus of said first processor type with an address bus of said integrated circuit;
- a third signal path to couple a third bus of said second processor type with said address bus of said integrated circuit;
- and
- selection logic to select between said second and said third signal paths based at least in part upon said identified processor type.
2 more elements
A control interface to be coupled to and transmit signals between a logic device and at least one of a first processor operating in accordance with a first protocol and a second processor operating in accordance with a second protocol, comprising:
- a first signal line to receive a read strobe signal and a transfer start indication signal;
- a second signal line to receive a write strobe signal and a read/write indicator signal to indicate read/write transactions;
- first selection logic to signal a write transaction to said logic device if said control interface is coupled to said first processor and said write strobe signal is received on said second signal line, or said control interface is coupled to said second processor and a transfer start indication signal is received on said first signal line and a write transaction is indicated by said read/write indicator signal on said second signal line;
- second selection logic to signal a read transaction to said logic device if said control interface is coupled to said first processor and said read strobe signal is received on said first signal line, or said control interface is coupled to said second processor and a transfer start indication signal is received on said first signal line and a read transaction is indicated by said read/write indicator signal on said second signal line;
- and
- programmable delay circuitry to dynamically delay said write transaction.
3 more elements
An apparatus comprising:
- a first interface to couple said apparatus to one of a plurality of host devices and a second interface to couple said apparatus to a second device,
- said first interface being equipped to interchangeably receive either multiplexed address and data signals from a first bus of a first host device of said plurality of host devices for transmission to an address bus and a data bus of said second device, or address signals from a second bus of a second host device of said plurality of host devices for transmission to said address bus of said second device and data signals from a third bus of said second host device for transmission to said data bus of said second device;
- and
- said first interface being further equipped to receive one or more control signals including a read strobe signal and a write strobe signal if said apparatus is coupled to one of said plurality of host devices operating in accordance with a first protocol, and to receive one or more control signals including a transfer start indication signal and a read/write indicator signal if said apparatus is coupled to one of said plurality of host devices operating in accordance with a second protocol.
1 more element
An apparatus comprising:
- a first interface to couple said apparatus to one of a plurality of host devices and a second interface to couple said apparatus to a second device,
- said first interface being equipped to interchangeably receive either multiplexed address and data signals from a first bus of a first host device of said plurality of host devices for transmission to an address bus and a data bus of said second device, or address signals from a second bus of a second host device of said plurality of host devices for transmission to said address bus of said second device and data signals from a third bus of said second host device for transmission to said data bus of said second device;
- said first interface being further equipped to receive one or more control signals including a read strobe signal and a write strobe signal if said apparatus is coupled to one of said plurality of host devices operating in accordance with a first protocol, and to receive one or more control signals including a transfer start indication signal and a read/write indicator signal if said apparatus is coupled to one of said plurality of host devices operating in accordance with a second protocol;
- first delay circuitry to programmably delay address signals to be transmitted to said address bus of said second device;
- and
- second delay circuitry to programmably delay write transactions to be transmitted to said second device.
3 more elements
A processor comprising:
- internal resources;
- and
- interface logic to selectively couple said processor to an interchangeable one of a plurality of host processors, by providing a first interface for connection to a first bus of a first host processor having a first architecture type, or a first and second bus of a second host processor having a second architecture type to provide a selected one of said first and second host processors with access to said resources.
Dependencies are inferred from the claim text.