US 6,841,811 B2Granted

Large area, fast frame rate charge coupled device

AssigneeFairchild Imaging

InventorsDavid Wen, Steve Onishi

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Abstract

Large area, fast frame rate, charge coupled devices (CCDs) are provided. Interline transfer CCDs can have interleaved pinned photodiodes and vertical shift registers. The interline transfer CCDs are ideal for producing high frame rate video images from a continuous light source. The photodiodes transfer charge indicative of the previous video frame to an adjacent vertical shift register with little or no lag, while light from the current video frame is integrating in the photodiodes. The charge signals only have to travel a short distance from a photodiode to an adjacent vertical shift register. The charge signals indicative of each video frame are then shifted out of the vertical shift registers. Each vertical shift register has a doping gradient that increases the charge transfer rate. All of these factors provide a fast and efficient video frame rate, even in a large area CCD.

Claims15

Dependent claims

An interline transfer charge coupled device comprising:

columns of pinned photodiodes formed in a semiconductor;
and
vertical shift registers interleaved in between each of the columns of pinned photodiodes,
wherein each of the vertical shift registers comprises:
(a) a first gate over the semiconductor, wherein a region of the semiconductor beneath the first gate has a first electric potential;
(b) a first doped region in the semiconductor next to the region of the semiconductor beneath the first gate, the first doped region having a second electric potential that is greater than the first electric potential;
(c) a second doped region in the semiconductor next to the first doped region, the second doped region having a third electric potential that is greater than the second electric potential;
(d) a third doped region in the semiconductor next to the second doped region, the third doped region having a fourth electric potential that is greater than the third electric potential;
and
(e) a second gate over the first, the second, and the third doped regions, the first gate being coupled to the second gate and to an electrode.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/641,640Filed 14 Aug 2003 · division
Priority: 16 Jul 2002
Published: US 2004/0014332 A119 Feb 2004
Granted: 11 Jan 2005
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/0198
Manufacture or treatment: integrating together multiple components covered by H10D44/00, e.g. integrating charge coupled devices
H10F 39/1534
Two-dimensional or three-dimensional array CCD image sensors: interline transfer
H10F 39/026
Manufacture or treatment of image sensors covered by group H10F39/12: wafer-level processing

Family

Application10/198,269Parent of this division · filed 16 Jul 2002
US 2004/0033656 A1Pre-grant publication · published 19 Feb 2004
US 2004/0014332 A1Published application
US 6,818,483 B2Related patent
US 6,841,811 B2This patent

From the US filing history. Foreign family members aren’t listed.